Agentic AI coding assistant

• Leading a scrum team in building an ML platform, collaborating with product managers, data scientists, and infrastructure engineers

• Fostered a collaborative and results oriented culture through mentoring, code reviews and design discussions

I spearheaded key initiatives to enhance the ML platform at C3 AI, leading to improved AI/ML application development and deployment.

• Designed and developed an end-to-end wrapper for OpenTelemetry tracing, streamlining debugging processes for LLM applications.

• Enhanced in-house DAG-based workflow orchestration increasing throughput, achieving auto-recovery and fault tolerance for various ML jobs (such as training, hyper parameter optimization and batch inference).

• Designed and led development of Model Registry and Experiment Tracking system, increasing transparency and collaboration in model development.

• Integrated APIs for enabling interpretation and scoring of DAG based ML pipeline towards explainability and evaluation of ML pipelines

• Summary - Developed Machine Learning and Deep learning models for enabling document information extraction, toward life insurance underwriting applications

• Machine Learning Software Engineering - Built robust data/feature pipelines, training pipelines, and metrics evaluation toward Machine Learning and Deep Learning model productization.

Created API endpoints in model serving platform, and testing docker images toward ML inference

• Applied Machine Learning - Identified requirements through cross-functional collaboration with product managers & data scientists, feature engineering, identifying model architecture through applied research, and training the models (AWS GPUs) for productization

• Summary - Extensive hands-on experience in ASIC design and validation, both as a Technical Lead and as an Individual Contributor, shipping production System Verilog code for multiple generations of Intel’s high-speed IOs

• Technical Lead - Designed and led implementation of on-chip built in self-test (BIST) for Intel's novel 3D IC integration technology. Reduced the design completion time by 3X, by automating code generation using templates. Mentored new college graduate engineers

• Individual Contributor - Experience in end-end design cycle of ASIC - RTL/logic design and coding, system validation, physical design, timing sign-off, and post silicon-debug, for Intel's next generation high speed serial interfaces. Successfully taped-out multiple IPs on latest technologies and characterized the performance.