# Ramya N. > Software Engineer, ML/AI Location: San Carlos, California, United States Profile: https://flows.cv/ramyan ## Work Experience ### Software Engineer @ Augment Code Jan 2025 – Present | Palo Alto, CA Agentic AI coding assistant ### Lead Software Engineer, ML Platform @ C3 AI Jan 2024 – Jan 2025 | Redwood City, California, United States • Leading a scrum team in building an ML platform, collaborating with product managers, data scientists, and infrastructure engineers • Fostered a collaborative and results oriented culture through mentoring, code reviews and design discussions ### Senior Software Engineer, ML Platform @ C3 AI Jan 2021 – Jan 2024 | Redwood City, California, United States I spearheaded key initiatives to enhance the ML platform at C3 AI, leading to improved AI/ML application development and deployment. • Designed and developed an end-to-end wrapper for OpenTelemetry tracing, streamlining debugging processes for LLM applications. • Enhanced in-house DAG-based workflow orchestration increasing throughput, achieving auto-recovery and fault tolerance for various ML jobs (such as training, hyper parameter optimization and batch inference). • Designed and led development of Model Registry and Experiment Tracking system, increasing transparency and collaboration in model development. • Integrated APIs for enabling interpretation and scoring of DAG based ML pipeline towards explainability and evaluation of ML pipelines ### Machine Learning Engineer @ Omniscience Corporation Jan 2019 – Jan 2021 • Summary - Developed Machine Learning and Deep learning models for enabling document information extraction, toward life insurance underwriting applications • Machine Learning Software Engineering - Built robust data/feature pipelines, training pipelines, and metrics evaluation toward Machine Learning and Deep Learning model productization. Created API endpoints in model serving platform, and testing docker images toward ML inference • Applied Machine Learning - Identified requirements through cross-functional collaboration with product managers & data scientists, feature engineering, identifying model architecture through applied research, and training the models (AWS GPUs) for productization ### Senior Hardware (ASIC) Design Engineer @ Intel Corporation Jan 2010 – Jan 2017 | Hillsboro, OR • Summary - Extensive hands-on experience in ASIC design and validation, both as a Technical Lead and as an Individual Contributor, shipping production System Verilog code for multiple generations of Intel’s high-speed IOs • Technical Lead - Designed and led implementation of on-chip built in self-test (BIST) for Intel's novel 3D IC integration technology. Reduced the design completion time by 3X, by automating code generation using templates. Mentored new college graduate engineers • Individual Contributor - Experience in end-end design cycle of ASIC - RTL/logic design and coding, system validation, physical design, timing sign-off, and post silicon-debug, for Intel's next generation high speed serial interfaces. Successfully taped-out multiple IPs on latest technologies and characterized the performance. ## Education ### Master's degree in Computer Science University of Illinois Urbana-Champaign ### MS in Computer Engineering Virginia Tech ### BE in Electronics & Communication PSG College of Technology ## Contact & Social - LinkedIn: https://linkedin.com/in/ramyanarayan --- Source: https://flows.cv/ramyan JSON Resume: https://flows.cv/ramyan/resume.json Last updated: 2026-04-10