# Reza Ahmadi

> AMS @ Meta | Analog Semiconductors, Circuit Design

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/rezaahmadi

With over 17 years of experience in analog semiconductors, circuit design, and mixed-signal development, I focus on advancing high-speed I/O links and AMS architecture. At Meta, I specialize in sensor fusion, camera and system architecture, D/C-PHY link optimization, and low-power chiplet die-to-die design to enable innovative and efficient solutions for next-generation technologies.  

My work integrates analog circuit design and mixed-signal expertise to create impactful advancements in display, camera, and sensor technologies that enhance connectivity and user experiences. Collaborating closely with internal and external stakeholders, I contribute to defining roadmaps and ensuring high-quality product development that aligns with Meta's mission of building immersive experiences.

## Work Experience
### AMS Architecture, Design and Management @ Meta
Jan 2022 – Present | San Francisco Bay Area
- Sensor fusion, camera and system architecture  
- D/C-PHY link design, optimization and development
- <0.5pJ/bit Chiplet Die to Die design, development and implementation

### Director of Engineering, Automotive PHY ADAS and IVI (AMS Design) @ Texas Instruments
Jan 2020 – Jan 2022 | Santa Clara, California, United States
- Customer and system focused design wins, definition of roadmap devices and core architecture for FPD-Link Automotive PHY IV, IV+), fab and technology selection 
- Design and product director responsible for product enablement from definition phase, pkg. selection and silicon tape out to silicon validation and customer enablement for FPD-Link ADAS and IVI
- Targeted architecture for high-performance sensor/Display-Cable gearbox including 
- CSI C/D-PHY, etc. link interfaces

### Display Design and Development @ Samsung Electronics America
Jan 2019 – Jan 2020 | San Jose, California, United States
- Silicon Design for Advanced Display Interconnect Technologies 
- Smart sensing and compensation for next generation 120Hz Displays

### AMS Sr. Design Manager, Chip Lead @ MACOM
Jan 2016 – Jan 2019 | Santa Clara County, California, United States
Focused product development and marketing  collaboration from MRD to system definition, sub-block specifications and deployment to internal design teams. Development and productization of DR4 modules and 112Gbps+ ADC/DAC-DSP solutions: 

- Highly visible role of co-designing with external customers, and delivery of internal and external executive updates 

- Leading AMS circuit and system design team:
Architecture and GDS delivery in AFE for 112Gbps+ ADC/DAC-DSP solution in single lambda products

- Major AFE re-architecture and silicon execution boosting JTOL margin and enhancing BER by 10x

### SMTS, Technical Lead @ Intel Corporation
Jan 2014 – Jan 2016 | San Jose, California, United States
- 28Gbps+ serdes development
- Sub-200fs/ low jitter and SONET compatible wide-band fractional synthesizer, digital PLL
- High performance digital CDR with improved INL

### Scientist, Senior Staff - Design @ Broadcom Inc.
Jan 2010 – Jan 2014 | Irvine, California, United States
First pass silicon and technology development for high performance SERDES:

- Broadcom's first 32Gbps+ SAR ADC based LR SERDES in 28nm 
- Broadcom's first extreme low phase noise 12GHz+ CMOS wide-band Fractional-N PLL
- Broadcom's first low power I/Q Gen. adopting Injection Locked Oscillator Clocking solutions for high performance digital CDRs
- 10Gbps Folded Flash ADC for LRM and MMF fiber
- Generic DFE based 28Gbps+ SERDES development for switch fabrics

### Senior Analog Designer @ Advanced Micro Devices
Jan 2009 – Jan 2010 | Boxborough, Massachusetts, United States
Circuits and architectures for high-speed memory interfaces

### Research Assistant (Analog Design Group) @ University of Minnesota
Jan 2004 – Jan 2009 | Twin-Cities
- 5Gbps receiver with ISI independent pilot-based clock and data recovery circuits for serial/parallel links 
- Constrained partial response signaling and equalization for 10-15Gbps chip-chip communication
- FEXT/NEXT crosstalk cancellation for chip-chip communication

### RF/Broadband Wireless Engineering Intern @ Qualcomm
Jan 2008 – Jan 2008 | Campbell, Santa Clara
Noise cancellation and design of wide-band fractional-N frequency synthesizers

### Engineering Intern @ Rambus
Jan 2007 – Jan 2007 | Mountain View
Clock and data recovery circuits for multi-tone signaling in wireline communication

### Co-Founder @ Hamyan Fan Electronics, Sharif University of Tech. Communication Circ. Lab Incubator
Jan 2000 – Jan 2002 | Tehran
DLC Modem Technology for Smart Grids:

- An FSK and OFDM Distributed Line Carrier (DLC) Modem product developed, successfully tested and commercialized for transmitting data over high-voltage distributing power lines. Fulfilled the need for smart grid in remote sensing/reading and actuating

- Analog mixed signal circuit design, system design and product development


## Education
### Ph.D. in Architectures and Circuits for High-Speed I/O Links
University of Minnesota

### MA.Sc in Clock and Data Recovery Circuits for Optical Communication (SONET-192)
University of Waterloo

### B.Sc in Electronics/ Electrical Engineering
Sharif University of Technology


## Contact & Social
- LinkedIn: https://linkedin.com/in/reza-ahmadi-1903a94

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Source: https://flows.cv/rezaahmadi
JSON Resume: https://flows.cv/rezaahmadi/resume.json
Last updated: 2026-04-13