# Rich Hankins > Founding Engineer Location: San Jose, California, United States Profile: https://flows.cv/richhankins I have broad experience developing high performance systems at many levels, from processor-cache-aware index structures, to runtime systems for experimental multi-core architectures, to distributed systems for free-text search. Specialties: Indexing, Search, Systems Development, Systems Performance, Relational Databases, Main Memory Databases, SQL, NoSQL, Python, C, C++, JavaScript, MapReduce, Web Services, API, Distributed Systems, Location based services, Mobile Services ## Work Experience ### Founding Engineer @ Augment Jan 2022 – Present | San Francisco Bay Area ### Creative Sabbatical @ Tontine Capital Jan 2022 – Jan 2022 | San Jose, California, United States ### Director Of Engineering, US @ MemVerge Jan 2021 – Jan 2022 ### Senior Software Engineer @ MemVerge Jan 2020 – Jan 2021 ### Software Engineer @ Pure Storage Jan 2011 – Jan 2020 ### Principal Research Scientist, Systems @ Nokia Research Center Palo Alto Jan 2006 – Jan 2011 2010 to Present: Member of the Mobile Computer Systems (MCS) team, an advance development team working on a new mobile platform. Projects include prototyping new system architectures and enhancing the mobile OS and software stack. 2006 to 2010: Member of the Context, Content, and Community (C3) team. Architect and developer, C3 Local Search project. C3 Local Search is a prototype next-generation search service that uses context-specific user data to rank and recommend local search results. Project included: · Designing index structures for quickly searching through large, heterogeneous data sets · Distributed service architecture for improved search performance · Distributed index construction to enable rapid prototyping and experimentation of new index structures Lead architect and developer, Nokia Simple Context (NSC) project. NSC is a system for collecting, aggregating, and indexing data actively recorded from a very large population of mobile devices. The system provides near real time access to the data being recorded from the population of mobile devices through a web-based API, which allows developers to create specialized applications for summarizing the data. Select design challenges for this system include: · Selecting efficient, scalable index structures for fast update and search operations · Supporting extensible data types and formats · Designing a web-based API for application developers · Developing a highly reliable client-side application for recording and managing data NSC is currently in use within Nokia for context-aware application development, user studies, and data collection. ### Research Scientist, Microarchitecture Research Lab @ Intel Jan 2004 – Jan 2006 Researched a multi-threading ISA for IA-32 processors, called the Multiple Instruction Stream Processor (MISP). The MISP ISA extension defines a set of instructions that allow an application program to directly manage user-level threads without OS intervention. In addition, MISP supports the cache-coherent shared-memory programming model, which greatly simplifies the program model by allowing an application to use the widely accepted multithreaded programming paradigm. Specific components of this project included: · Worked with product groups to analyze the programming model and software support · Constructed a prototype MISP processor using custom firmware executing on a physical IA-32-based multiprocessor system · Developed the software runtime system for application development · Ported several commercial software application programs to execute on our prototype system ### Graduate Research Assistant @ University of Michigan Jan 2000 – Jan 2004 Designed an architecture-conscious database management system, called Quickstep, which is optimized for the main-memory environment. As part of this effort, I developed a flexible data storage model that efficiently utilizes the processor cache under a variety of query workloads. I also investigated the microarchitectural effects of index node size on the performance of cache-conscious indexes. Designed a scalable Suffix Tree indexing algorithm for processing very large string data. The algorithm traded algorithmic complexity for better main-memory and disk utilization, resulting in much better practical performance on commodity hardware, and allowed us to scale workload sizes to much higher levels than previously published. This work was in addition to my dissertation on architecture-conscious storage management. ### Graduate Research Intern Microarchitecture Research Lab @ Intel Jan 2003 – Jan 2003 Characterized the microarchitectural behavior of large-scale, server workloads, including online transaction processing (OLTP) and decision support systems (DSS). This work focused on the microarchitectural behavior of OLTP workloads as the size of the workload scales. ## Education ### Ph.D in Computer Science; Database Management Systems University of Michigan ### BSc in Electrical Engineering Kettering University ### Master of Science in Electrical Engineering Kettering University ## Contact & Social - LinkedIn: https://linkedin.com/in/richhankins --- Source: https://flows.cv/richhankins JSON Resume: https://flows.cv/richhankins/resume.json Last updated: 2026-04-10