# Rocco Tangorra

> Former Lead Principal Engineer at Infineon

Location: San Jose, California, United States
Profile: https://flows.cv/roccotangorra

DIGITAL AND LOGIC DESIGN ENGINEER
Digital logic design expert and team leader. Successful history of leading multi-site global logic teams in the development of digital IC designs and firmware for both logic IP development and logic-on-top SOC mixed-signal designs. Significant experience in RTL design, synthesis, timing closure, analog IP integration, traditional and UVM verification. Responsible for complete product life cycles, including product definition, feasibility, algorithms, design, test, and production ramp with a demonstrated history of first silicon success. 
Proficient single level and multi level NVM arrays behavioral models, with file system based initialization structures.

DIGITAL VERIFICATION UVM BASED EXPERIENCE
UVM based environment development.  Successful history of IP verification environment development: definition of different env components (driver, monitor, scoreboards), interconnection and virtual interfaces with RTL under test, definition of sequences and sequencers; building of coverage structures (cover groups and cover points), given the design requirements for functional coverage.
UVM based test cases development. Proficient test case writing, with different levels of randomization and interdependent constraining.  
Development of SystemVerilog based IP designs and Verification test benches, mainly focused on Non-Volatile Memory behavioral model array definition, different Read/Margin/Write algorithm implementation, RTL development of control logic

## Work Experience
### Lead Principal Engineer @ Infineon
Jan 2020 – Jan 2025 | San Jose, California, United States

### Principal MTS Design Engineer @ Spansion
Jan 2011 – Jan 2025

### Sr. MTS Design Engineer @ Spansion
Jan 2006 – Jan 2011

### Sr. Design Engineer @ Lattice Semiconductor
Jan 2004 – Jan 2006

### Sr Designer - Design Manager @ Azalea Microelectronics
Jan 2001 – Jan 2004 | Santa Clara, CA

### Designer @ Tower Semiconductor
Jan 1998 – Jan 2000

### Designer @ Tecnopolis CSATA Novus Ortus
Jan 1990 – Jan 1998


## Education
### MS in Electrical and Electronics Engineering
University of Bari


## Contact & Social
- LinkedIn: https://linkedin.com/in/rocco-tangorra

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Source: https://flows.cv/roccotangorra
JSON Resume: https://flows.cv/roccotangorra/resume.json
Last updated: 2026-04-13