# Rohit Priyadarshi > Principal Software Engineer at Arteris, Vice President at Stealth Startup, Independent Consultant (Electronic Design Automation) Location: Fremont, California, United States Profile: https://flows.cv/rohitpriyadarshi Versatile Technologist with Extensive Startup Experience Resourceful problem solver and seasoned entrepreneur with a background in founding startups spanning Internet, AI, IoT, and custom hardware industries. Proficient in building complex software systems for Electronic Design Automation (EDA) targeting diverse chip architectures including FPGAs, ASICs, Structured ASICs, and superconducting chips. Skilled in C, C++, and algorithm development, with a deep understanding of EDA workflows and FPGA prototyping platforms. Demonstrated leadership in guiding multidisciplinary teams towards innovative solutions for open-ended challenges. Experienced in navigating the highs and lows of startup ventures, leveraging setbacks as opportunities for growth. A programming language agnostic with a passion for tackling complex technical problems head-on. ## Work Experience ### Principal Software Engineer @ Arteris Jan 2024 – Present | United States ### Co-Founder @ Stealth Startup Jan 2021 – Present | Fremont, California, United States • IoT Startup for System Control: Developed an embedded remote access system enabling users to control reference boards securely through hardware-level separation between controller and controlled interfaces. • IoT Startup for AI-Based Machine Condition Monitoring (FPGA): o Engineered an edge compute system for fault detection in machines, leveraging DSP and machine learning algorithms. o Designed and implemented a router-like hardware framework for Raspberry Pi to onboard sensor data. o Developed temperature sensor driver using Python for Analog Devices (ADT7420) and integrated it with MATLAB’s ThinkSpeak cloud platform. o Implemented Verilog algorithms on MYiR Tech’s Z-Turn Board with Xilinx’s Zync 7020 chipset to detect faults in real-time based on Hilbert Huang algorithm. o Prototyped Bearing Analysis in MATLAB with GUI using AppDesigner and designed bearing animation using Fusion 360 for status feedback. • Startup for Printing Devices: Designed and built a prototype for utility patents using Arduino Uno, InkShield, USB Shield, and optical sensors. Designed optical sensor fusion PCB using CadSoft Eagle 7+. • Startup for Shared Economy (Foodsie Inc.): Co-founded a company and developed websites on AWS and Google cloud platform using Magento. Integrated Braintree for payment processing, Twilio for SMS notification, Mailgun for email handling, and Template Monster for custom skins. • Startup for Matchmaking (VirtualSamaj): Developed matchmaking and social networking website using Boonex’s dolphin. Created matchmaker plugin for astrological data. • Startup for Micro-Satellites: Initiated a CubeSat project to address internet access issues in remote regions. Considered launch with Indian Space Research Organization (ISRO). • Startup for Vaccine Distribution: Designed PCB designs for ColdChain-IoT to track vaccine refrigeration and proposed blockchain integration for certification. ### Independent Consultant, Electronic Design Automation @ Unknown Jan 2021 – Present | Fremont, CA, United States • EDA Architect leading inception and development of cutting-edge tools as consultant at Pico2Femto Ltd. • Android BLE App development for GPX10 AI chip by Ambient Scientific Inc. • High-Performance Computing: Invented methods to linearly accelerate graph algorithms on PlayStation 3 and built experimental applications using ATI's stream processors. • Open-Source Effort: Developed a comprehensive data-model for Electronic Design Automation licensed under MIT. • Software Projects: Created a Mathematical CAD package, DiskView package for viewing hard disks sector by sector, Windows library, sound generator for DSP research, and solutions manual for "Programming with C" by Byron S. Gottfried ### EDA Software Engineer @ Intel Corporation Jan 2021 – Jan 2024 | San Jose, California, United States • Managed and integrated eASIC's eTools for RTL to GDSII, involving Synopsys tool chain integration with eASIC place and route. • Led the eTools team and represented them in the development of next generation eASIC product families, collaborating across multiple teams from design to manufacturing. • Created proposals and collaborated with the Project Manager to develop eTools schedules, ensuring effective project planning and execution. • Served as the primary point of contact for resolving complex technical issues, leveraging expertise across various domains to address challenges and ensure project success. • Played a key role in problem-solving across the eTools tool chain and Quartus Prime components, ensuring a cohesive workflow from FPGAs to eASIC. • Designed multiple architectural components and contributed to the development of the next generation of Quartus Prime. • Conducted comprehensive analytics and data mining on Quartus data access patterns to optimize workflow efficiency. • Championed innovation by developing a Generative AI PoC, empowering teams to streamline workflows and enhance productivity through natural language-enabled compiles. • Crafted an AI-driven data extraction system encompassing web scraping and customized infographic extraction capabilities. ### ASIC Electrical Design Automation (EDA) Software Architect and Group Leader @ Northrop Grumman Jan 2019 – Jan 2021 | Baltimore, Maryland Area Switched from Semiconductors to Superconductors. • Built superconducting Reciprocal Quantum Logic (RQL) cell library integration methodology into custom place & route tool, along with feature enhancements. Implemented P&R and library build automation for local consumption. Distributed compute in Python to generate gate variants and run the entire flow to DRC including timing, device compute and report visualization in web browser. Design and specification to fully revamp RQL library management system via prior work on EDA centric common data model to embed EDA tools and optimize design flows. Revamped the codebase under C++11/17 with cmake build system and comprehensive Python bindings using SWIG. Relicensed it under MIT to make it freely available. Optimized RQL STA engine for runtime by 80x and mentored the team to optimize memory by 300x. Built training material for development of synthesis tools along with majority-3 based synthesis study. ### Senior Principal Software Engineer @ Cadence Design Systems Jan 2016 – Jan 2019 | San Jose, California Compile time performance improvement using sqlite database. Automated insertion of SerDes IP on QSFP connectors. Pre-synthesis and insertion of multiplexor blocks in Protium ASIC prototyping system. Rebuilt TDM circuitry in Verilog for pre-synthesis using Xilinx Vivado. Replaced hardcoded TDM circuit generation with pre-synthesized circuitry. Architected MVC based backend system with design of all editors. Built JSON based client server model, hardware configuration editor with JSON database, terminal assignment editor, LSF job management system, compiler results manager, design metric manager. ### Sr. MTS @ Atoptech Jan 2012 – Jan 2016 | Santa Clara, California Achieved between 30%-40% compression of floating point timing-delay-tables using C++ templates without API changes to allow seamless integration into the timing engine. Revamped the location query engine for placement and optimization. More than 300 issues resolved since joining related to floor-planning, pin-assignment, placement, routing, database engine and command- interface, with various levels of complexity. ### Design Engineer, Sr. MTS @ Altera Jan 2010 – Jan 2012 Analyzed and solved numerous critical issues in TimeQuest. A few examples are: SDC translation between FPGA and HardCopy, precision loss in timing calculation, SDC workarounds for incorrect timing models leading to silicon failure. Mentored TimeQuest team members on a regular basis related to algorithmic improvements, out of which two ideas are being pursued for patent. Design and implementation of XML variables database in Perl as a replacement of proprietary file format. Fixed issues related to inconsistent multithreading behavior and upgraded deprecated system functions. Design and implementation of control variables backend and flow control in the upcoming Partial Reconfiguration feature in Quartus II including presentations, tutorials and demos for customers and applications team. ### Sr. Staff R&D Engineer / Sr. Manager @ Synopsys Jan 2008 – Jan 2010 Architected the new tool flow that decoupled the GUI from the backend software. Occasional field visits to tackle difficult customer issues and take them to conclusion. Invented a new state-based method for automated tool flow control, forming a new basis for software architecture. Architected and tweaked the model-based area estimation and incorporated area-flow based mapper for area-estimation. Invented and implemented symbolic IO usage algorithm based on the symbolic tree that uses computations instead of actual netlist, achieving several orders of magnitude improvement in runtime making what-if analysis practical for the users. ### Senior Staff Engineer / Director @ Synplicity Inc. Jan 2002 – Jan 2008 Invented a new method to improve the performance of Time Division Multiplexing circuitry across chips improving throughput. Developed High-Speed-Time Division Multiplexing reset logic circuit, insertion of Time Division Multiplexing. Implemented time-budgeting, signal-handling, netlist-editing, mapper-split-flow capabilities and methodology to handle complex data-types in VHDL writer after partitioning. Specifications, design and implementation of light weight symbolic tree data-structure to virtually uniquify netlist, which became the primary netlist interface for several tools. Championed and implemented the unification of synthesis engine across products, cutting the support cost in 1⁄2. Lead the effort on board vendor relations and requirements for RTL partitioner and numerous customer visits to solve complex issues in the field. ### Senior Software Engineer @ Zenasis Technologies Jan 2002 – Jan 2002 Implemented incremental timing analysis engine in two weeks. Invented a new algorithm for pin-ordering to speed-up the incremental timing analysis engine. ### CAD Software Engineer @ Prolific Inc. Jan 2001 – Jan 2002 Design and implementation of library estimation and block optimizer tool to generate enhanced libraries. Setup Cadence SE-PKS and Colorado Framework for high performance designs to validate liquid cell methodology. Implemented design flow using Magma Blast Fusion for liquid library. Resynthesized Virtual Silicon Technology 0.13 library as purported by Blast Wrap to validate Magma's ability to use additional cells in the library. ### Project Leader @ Sycon Design Inc. Jan 1998 – Jan 2001 Played pivotal roles in design and implementation of key software components to usher Sycon tools from scripting prototypes to industrial strength EDA tools. Set up companywide software development framework and C++ coding guidelines and conventions and encoded them into C++ code generator. Specification, design and implementation of the entire software backend core to effectively represent design data along with extensive functionality in 1/4 the estimated time by building and using custom C++ code generator that generated 25000 lines of code from 500 lines of symbolic code to meet schedule. Design and implementation of GUI backend for two dimensional region query display and highly optimized matrix transformation system that enabled Sycon to correctly display hierarchical layout with arbitrary translation, 90° rotation and zoom factors. Design and implementation of Delay Calculation Engine and timing driven capability for the relative placement engine based on modified iterative minmax pert algorithm for slack distribution, proprietary final placement engine using topological heuristics for the overlap removal and compaction honoring prior relative placement. Invented a binary interval tree data structure to help in the overlap removal problem. Guided a team of two engineers to implement transistor level extensions to backend to implement and integrate Liberty, LEF, DEF, CIF parser, GDSII and Spice compiler and GUI team towards implementation of GUI using common database. ### Senior Software Engineer @ Viewlogic Systems Inc. Jan 1996 – Jan 1998 Specification, design and implementation of Electronic-Design Data Store (EDS). Provided guidance for enhancements to EDS, including persistence mechanism. Provided full support to the group utilize the capabilities of EDS. Wrote a LEF parser in C++ to complete the flow temporarily. Added Auto-Grouping capability to the auto-floorplanner. It generates initial physical hierarchy automatiacally, based on the clustering of cells depending on logical hierarchy and gate equivalent size. Added several other clustering operations that were used by auto-floorplanner. Provided support for rectilinear block handling to auto- floorplanner. Enhanced the global router to handle design hierarchy. ### Senior Software Engineer @ COMPASS Design Automation Jan 1996 – Jan 1996 Enhancements and maintenance of ChipPlanner and PathFinder. Contributed to the RTL floorplanning, path delay calculations and netlist I/O. Support to handling of flexible blocks in the RTL flow. Support to the Pack and Shape and Abut and Spread commands, which were based on topological constraints reduction. Benchmark the new MakeTIME and FixTIME commands. Fixed a number of bugs. ### Member Technical Staff @ HCL America Jan 1995 – Jan 1996 Consulting, porting, testing, test suit writing and building of software products. ### Senior Software Engineer @ Usha Matra Ltd. (A division of Matra MHS, France) Jan 1992 – Jan 1995 Specification, design of an Interactive Layout Editor. Implemented most of the code. Implementation was in C++. Implemented GUI using Xlib and Motif. Implemented a fast two dimensional region query algorithm based on HV/VH tree data structure to enable a fast interactive response. ### Electronics Engineer @ Department of Physics, AMU, India Jan 1989 – Jan 1992 Specification, design and development of a number of software projects to help research students and teachers in their work. It includes a Mathematical CAD software which had the capability to calculate and plot mathematical equations, a DiskView software that allows inspecting a disk drive, a Windows library to help build software projects, a solutions manual for “C” language, generation of sounds to help in DSP research and more. ### Management Trainee @ Philips India Jan 1988 – Jan 1989 Training in audio and video electronics. Training on Computers. On-call expert for fixing equipment that could not be fixed by any technition. ## Education ### NDO in Electrical Engineering Stanford University ### Continuing Education in Computer Science American Sentinel College ### BSEE in Electrical Engineering (Microelectronics) Aligarh Muslim University ## Contact & Social - LinkedIn: https://linkedin.com/in/rpriyadarshi - Portfolio: http://www.altera.com - Portfolio: http://www.atoptech.com - Portfolio: http://www.synopsys.com --- Source: https://flows.cv/rohitpriyadarshi JSON Resume: https://flows.cv/rohitpriyadarshi/resume.json Last updated: 2026-04-12