Customer enablement and debugging for edge inference solutions based on the Movidius Keem Bay chip (vision processing unit including camera pipeline and neural network accelerators)

Support, hands-on and debugging of Linux on Arm (Yocto build).

Program SHAVE vector processor adding functionality missing in Neural Network accelerator.

Technical-Lead current generation Imaging Processing Unit (IPU3). Responsible for analyzing new feature requests (feasibility and performance). Providing support (bug analysis & fixing) together with Windows/Android driver team for camera related issues.

Feature implementation and bug fixing for next generation Imaging Processing Unit (IPU4). Pre-silicon validation on FPGA system, co-debugging with HW-team.

Feature-lead "RGB-IR sensor support". A FW extensions that enables IR-extraction and RGB restoration from a “hybrid” RGB_IR sensor. Responsible for technical design, performance analysis, validation plan, planning and project execution (scrum). Project size 2 MY, 3-5 engineers.

Translating Algos to a model that represents the bit-exactness of the final FW/HW implementation. These models also contain instrumentation used as input for performance analysis. Both Algo and model were done in C++ in a Intel proprietary simulation environment.

Part of Klocwork waiver committee.

Feature enhancement existing Image Processor (IPU1) with new FW and SW.

FW development (design/implementation) for next generation Image processor (IPU3).

Power-on IPU3 Silicon and co-debugging with HW team

Scrum master

Takeover from NXP Digital Television group

Technical lead in a 240Hz video back-end solution based on dual 120Hz solutions (each processing a left and right stripe). Major restructuring of Streaming Layer (core component) was required to accomplish the necessary synchronization

Extend video back-end firmware to support 3D television.