Santa Clara, CA, United States
Technical-Lead current generation Imaging Processing Unit (IPU3). Responsible for analyzing new feature requests (feasibility and performance). Providing support (bug analysis & fixing) together with Windows/Android driver team for camera related issues.
Feature implementation and bug fixing for next generation Imaging Processing Unit (IPU4). Pre-silicon validation on FPGA system, co-debugging with HW-team.
Feature-lead "RGB-IR sensor support". A FW extensions that enables IR-extraction and RGB restoration from a “hybrid” RGB_IR sensor. Responsible for technical design, performance analysis, validation plan, planning and project execution (scrum). Project size 2 MY, 3-5 engineers.
Translating Algos to a model that represents the bit-exactness of the final FW/HW implementation. These models also contain instrumentation used as input for performance analysis. Both Algo and model were done in C++ in a Intel proprietary simulation environment.
Part of Klocwork waiver committee.