Trained in Artificial Intelligence and Machine Language. Trained and hands on in Python coding. ASIC Physical Design Consulting engineer, self-motivated electrical engineer (MSEE) with over 23+ years of diverse experience in electrical engineering, IP sales, business management, project management, IC chip physical design, Engineering Design Automation (EDA) software development, EDA tool integration, ASIC design methodology, physical sciences research. Over 10+ taped out designs using leading edge technology from IBM and TSMC using market leader EDA tools such as IBM, Cadence, Synopsys and MAGMA. Active consultant ASIC physical design and methodology development and practical in-depth knowledge of the leading EDA physical design tools from Cadence, MAGMA and Synopsys and associated tools flow. End clients: Meta, Synopsys, Broadcom, GOOGLE, Astera Labs, INTEL, etc.

Interested in working with bleeding edge process technology, physical design and methodology development and related technical business, marketing and sales managing.

Specialties:

* Artificial Intelligence and Machine Language

* Python Programming, Cornell Certification

* APPLIED MACHINE LEARNING AND AI, Cornell Certification (WORKING)

* ASIC Physical Design

• ASIC Design Methodology Development

* ASIC Power Methodology

Consulting at ASTERA LABS,INC. Sunnyvale, California

• Tools: ICC2, ICV, VUE, Sed/AWK, TcL, Makefile

• Process: TSMC **CONFIDENTIAL ***

• Std Cell Library: TSMC

• Completed work: Urgent, right before tapeout, DRC, LVS, ANT verification, repair

Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc.
 The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom libraries. All work is being done at the top level. The work includes doing DRC checking using SYNOPSYS icv and icwbev. I cannot discuss the detail, but all is very exciting.

Hired to consult on-site for Intelliswift as a Senior Physical Designer. This included 10nm technology, place and route, using INTEL design flow, EDA tools by Synopsys (for example ICC2), project management and floorplanning exploration and timing convergence and deliver a floorplan that includes 4 large each 2 million gates blocks. Project also included, documentation of tasks, status reports and meetings.