# Ruben R. > Principal ASIC Physical Design Engineer Consultant at Athena Cloud Engineers, Inc. Location: San Francisco Bay Area, United States Profile: https://flows.cv/rubenr OPEN FOR WORK. Completed a two contract. Process 3nm. RTL2GDS. ASIC Power/Physical/Methodology Design Engineer. Trained in Artificial Intelligence and Machine Language. Trained and hands on in Python coding. Experienced in ASIC Physical Design Consulting engineer, self-motivated electrical engineer (MSEE) with over 23 years of diverse experience in electrical engineering, IP sales, business management, project management, IC chip physical design, Engineering Design Automation (EDA) software development, EDA tool integration, ASIC design methodology, physical sciences research. Over 10 taped out designs using leading edge technology from IBM and TSMC using market leader EDA tools such as IBM, Cadence, Synopsys and MAGMA. Active consultant ASIC physical design and methodology development and practical in-depth knowledge of the leading EDA physical design tools from Cadence, MAGMA and Synopsys and associated tools flow. Interested in working with bleeding edge process technology, physical design and methodology development and related technical business, marketing and sales managing. Specialties: • Artificial Intelligence and Machine Language *. Python, Cornell Certification (complete Jan 2024) * AI & ML, Cornell Certification (complete June 2024) *. ASIC Physical Design • ASIC Design Methodology Development ## Work Experience ### Principal ASIC Physical Design Engineer Consultant @ Athena Cloud Engineers, LLC Jan 2019 – Present | Sunnyvale, California Trained in Artificial Intelligence and Machine Language. Trained and hands on in Python coding. ASIC Physical Design Consulting engineer, self-motivated electrical engineer (MSEE) with over 23+ years of diverse experience in electrical engineering, IP sales, business management, project management, IC chip physical design, Engineering Design Automation (EDA) software development, EDA tool integration, ASIC design methodology, physical sciences research. Over 10+ taped out designs using leading edge technology from IBM and TSMC using market leader EDA tools such as IBM, Cadence, Synopsys and MAGMA. Active consultant ASIC physical design and methodology development and practical in-depth knowledge of the leading EDA physical design tools from Cadence, MAGMA and Synopsys and associated tools flow. End clients: Meta, Synopsys, Broadcom, GOOGLE, Astera Labs, INTEL, etc. Interested in working with bleeding edge process technology, physical design and methodology development and related technical business, marketing and sales managing. Specialties: * Artificial Intelligence and Machine Language * Python Programming, Cornell Certification * APPLIED MACHINE LEARNING AND AI, Cornell Certification (WORKING) * ASIC Physical Design • ASIC Design Methodology Development * ASIC Power Methodology ### Principal Consultant @ Self-employed Jan 2018 – Present | San Francisco Bay Area ### ASIC Physical Design Engineer @ Mobiveil Inc. Jan 2019 – Jan 2019 Consulting at ASTERA LABS,INC. Sunnyvale, California • Tools: ICC2, ICV, VUE, Sed/AWK, TcL, Makefile • Process: TSMC **CONFIDENTIAL *** • Std Cell Library: TSMC • Completed work: Urgent, right before tapeout, DRC, LVS, ANT verification, repair ### Design Automation Engineer consultant @ Intel Corporation Jan 2017 – Jan 2018 | Santa Clara Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc.
 The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom libraries. All work is being done at the top level. The work includes doing DRC checking using SYNOPSYS icv and icwbev. I cannot discuss the detail, but all is very exciting. ### ASIC Senior Physical Design Engineer Consultant @ Intel Corporation Jan 2016 – Jan 2017 | Santa Clara Hired to consult on-site for Intelliswift as a Senior Physical Designer. This included 10nm technology, place and route, using INTEL design flow, EDA tools by Synopsys (for example ICC2), project management and floorplanning exploration and timing convergence and deliver a floorplan that includes 4 large each 2 million gates blocks. Project also included, documentation of tasks, status reports and meetings. ### ASIC Physical Designer Consultant @ Qualcomm Jan 2016 – Jan 2016 | Santa Clara, CA Contracted to do synthesis/floorplanning/place and route/cts/static timing analysis/extraction/LVS/DRC/DFM. Challenge, to improve performance of a taped out design. Technology is 180nm and EDA tools are Cadence/Synopsys/Mentor Graphics. ### Senior ASIC Physical Design Engineer Consultant @ Eximius Design Jan 2016 – Jan 2016 | Mountain View, CA Contracted to take a soft IP and harden it by taking the synthesized netlist through place and route and qualifying it using timing reports and physical verification. Automated the design and tools flow by scripting the environment. The EDA tools are Cadence Innovus and the technology is TSMC 16nm using the Avago 16nm standard cell library. The harden IP is over 20 million gates. ### ASIC Physical Designer (consultant) @ Broadcom Jan 2015 – Jan 2016 | Sunnyvale, California Contracted to do full chip static timing analsys and physical design. Deliverables are scripts to help analyze timing relation issues and solutions to timing violations. I worked with other timing engineers to help converge on timing at the full chip. Analyzed timing reports from Cadence Tempes and Place and route scripts from ATOP Technologies. ### Technical Marketing Engineer Consultant @ PNY Technologies Jan 2014 – Jan 2015 | San Jose, California Write technical collaterals: datasheets, app notes, white papers, product briefs, technical product training materials to help train sales and marketing team and establish quicker adoption of PNY SSD products. Work with content experts to define gaps in existing content, and develop appropriate content solutions addressing the needs. Work with cross functional teams to characterize PNY SSD, performance benchmark and generate collateral to help competitive positioning of the product and to communicate the value. Manage and help drive third party reviews and validations of competitive technical data including at application and synthetic test level. Support Marketing and Business Development efforts to broaden the customer base, support design win-design-in opportunities. Develop demos, proof points etc. for roadshows to establish product goodness and showcase user perceivable value additions. Lead discussion panels at conferences and industry group events and/or product shows. ### MTS (Member of Technical Staff) Design Engineer @ AMD Jan 2013 – Jan 2014 | Sunnyvale, California • Technical member of the SERDES1 IP design team. • Using process down to 20nm. • Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. • Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. • Application of circuit design or logic optimization to converge on timing. • Responsible for physical design implementation of complex SoCs. • Participating in physical design methodologies and flow automation. • Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. • Writing scripts in SED, AWK, Python, Tcl and Perl. ### ASIC Physical Design Engineer Consultant @ AMD Jan 2011 – Jan 2013 | Sunnyvale, CA Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. Using process down to 28nm. Application of circuit design or logic optimization to converge on timing. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing scripts in SED, AWK, Tcl and Perl. ### Senior Physical Desgn Engineer Consultant @ Synapse Design Automation Inc. Jan 2011 – Jan 2011 | San Jose, CA Using Synopsys ICC & Primetime, MAGMA Talus, Mentor Graphics Calibre, and Cadence SOC Encounter. Using process down to 40nm. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing scripts in SED, AWK, Tcl and Perl. ### Business Manager Consultant @ ChipStart Jan 2011 – Jan 2011 | San Jose, CA Responsible for identifying, qualifying and closing IP sales opportunities for ChipStart, LLC in Northern California (Silicon Valley). Achieve revenue targets. Manage relationships at management & operational levels with customers and partners. Sales forecasting with high degree of accuracy. Understand customer needs/expectations and decision making process. Identify and qualify projects. Build accurate pipeline to manage priorities and provide forecast. Define account plans and execute them through effective planning of resources. Present proposals, manage negotiations and close the sales. Gain strategic information about customers and the industry to help anticipate market trends. Participation in trade shows, client conferences, industry events, etc. Partner with and develop key relationships with Regional head (management), Business Team (product marketing, product specialist), and Professional Services (pre and post sales support). Build and leverage relationships with existing and potential customers and partners. Use of CRM tools. Track and provide feedback on quality of leads. ### Engineering/Sales/Business Development Consultant @ Ruben Reyes Jan 2011 – Jan 2011 | Sunnyvale, CA Strategic Consulting, including business plan & sales strategy development. ### Principal Engineer and Founder @ Trivium Tech Force Corporation Jan 2010 – Jan 2011 | Sunnyvale, CA • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization. • Work with sales team to negotiate and close contracts for IP based products. • Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements. • Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information. • Gain working knowledge of partner technical and business strengths, target markets ### Principal Engineer and Founder @ Global Trivium Corporation Jan 2009 – Jan 2010 | San Jose, CA • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization. • Work with sales team to negotiate and close contracts for IP based products. • Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements. • Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information. • Gain working knowledge of partner technical and business strengths, target markets ### IC Physical Design Engineer & Project Management Consultant @ Ruben Reyes Jan 2008 – Jan 2009 | San Jose, CA Recommended and experience is developing designs flows from synthesis to tape-out GDS in Synopsys, Cadence and MAGMA using 65nm process nodes and higher. Including the proven ability to manage projects, interview, qualify and hire design engineers. ### Senior Design Engineer @ QThink Jan 2004 – Jan 2008 | San Jose, CA * ASIC Physical Design from netlist to GDSII. * ASIC Design Methodology Development. * Tools flow development and evaluation. * Worked with Sales in new development deals for new business opportunities. * Developed brand strategies with Sales. * Strategic Consulting, including business plan & sales strategy development for start-ups. ### Staff Corporate Applicaton Engineer @ Synopsys Jan 1998 – Jan 2003 | San Jose, CA Support customers using Astro/Physical Compiler/other backend tools from Synopsys Support R&D in tool testing and developement Support Coprorate Application Engineers. Develop test plans Develop product features Develop tools flows and design methodologies ### Senior Design Consultant @ Cadence Design Systems Jan 1993 – Jan 1998 | Long Island, NY Physical design using Cadence Virtuoso, CELL3, Preview, taped out designs using Silicon Ensemble, LEF&DEF, SED&AWK scripting, Floorplanning, Place&Route, using 0.35um process, design methodology development and assessment, EDA support for Silicon Ensemble and DRACULA. ### Engineer @ IBM Thomas J. Watson Research Center Jan 1982 – Jan 1993 | Westchester, NY * Touch screen research & product development. * Worked on IBM's leading edge submicron technology in custom physical design & methodology. * Worked on several IBM chips and products: PowerPC 630 chip, TouchSelect, 4055 Infowindows, 8516 Touchscreen, and the Advanced Technology Classrooms, & systems on a chip(ASIC). * Worked with IBM's leading edge submicron technology (cmos5x and cmos7) in custom physical design. As well as setting up a design methodology for measuring performance when doing custom physical design. * Designed a custom 64-bit register, using IBM technology, hard block for a CPU chip for the datapath. Using cmos5x, 0.25micron IBM technology. Physical design and verification (IBM Niagara and Cadence Dracula). * Created and lead in establishing one way of doing remote verification for his custom physical design team. * I took an intensive CMOS design course by IBM and instructors from Columbia, Cornell, and MIT. * Co-authored several IBM white papers. ## Education ### MSEE in Control Systems New York University - Polytechnic School of Engineering ### BSEE with Honors in Electrical Engineering Pratt Institute ## Contact & Social - LinkedIn: https://linkedin.com/in/myresumerubenreyes - Portfolio: https://www.RubenReyes.com --- Source: https://flows.cv/rubenr JSON Resume: https://flows.cv/rubenr/resume.json Last updated: 2026-04-13