# Sananda Ghosh > Director of Products@Marvell Technology for AI & Datacenter | Engineering Leader | Product Management, Architecture & Strategic Planning | Semiconductor Hardware | EB1A Location: San Francisco Bay Area, United States Profile: https://flows.cv/sananda With a solid background in product management and computer architecture, my role as Technical Director of Product Line and Program Management at Marvell Technology is focused on co-development of critical custom silicon products for key Hyper-scaler customers . Previously, my role as Product Line Leader at Analog Devices centered on propelling the growth of the processor portfolio business to lead the Intelligent Edge market. Leading the charge in new product ideation and ensuring our offerings align with customer roadmaps, I was the linchpin for technical collaboration, accelerating investment, and identifying IP synergies. Prior to ADI, I was at Intel Corporation as a Senior Staff Product Line Manager where I honed my skills in defining complex hardware features and optimizing product portfolios for Xeon processors. This experience solidified my ability to work across technical and business boundaries, creating solutions that drive efficiency and position our products at the forefront of the industry. ## Work Experience ### Director of Technical Products & Program Management @ Marvell Technology Jan 2025 – Present | Santa Clara, California, United States ### Lifetime member of Beta Gamma Sigma -The International Honor Society for Business Graduates @ Beta Gamma Sigma Jan 2020 – Present ### Product Line Leader - Americas Region @ Analog Devices Jan 2023 – Jan 2025 | San Francisco Bay Area In my role as Product Line Leader in the Field at Analog Devices focusing on the processor portfolio, I serve as the point technical contact for regional sales teams, leading cross-functional teams to develop and launch new products that meet customers' needs. I collaborate with technical and business leaders to identify areas for investment and IP synergies, and maintain key customer relationships to support sales pipeline growth and technical training efforts. ### Senior Staff Product Line Manager @ Intel Corporation Jan 2022 – Jan 2023 | Santa Clara, California, United States In my role as a Senior Staff Product Line Manager at Intel Corporation in Santa Clara, California, I provided technical expertise for next-gen initiatives, optimized product portfolios, and led cross-functional teams to implement features based on customer requirements and business objectives. ### Staff Product Line Manager & Architect @ Intel Corporation Jan 2020 – Jan 2022 | Santa Clara, California, United States In my role as Staff Product Line Manager & Architect at Intel Corporation, I strategized and led critical architectural transformation initiatives to define and bring to market next-generation server products. I collaborated with business units to standardize XPU protocols, including CXL, across various segments. Additionally, I managed a cross-functional team to create consensus on product requirements and drive efficiency improvements in silicon design. ### Senior Product Line Architect & Technical Lead @ Intel Corporation Jan 2016 – Jan 2020 | Santa Clara, California, United States Product Architect, leading the architecture of several global infrastructure components of Intel's next gen flagship server processors. ### Product Architect & Technical Lead @ Intel Corporation Jan 2014 – Jan 2016 | Santa Clara, California, United States Processor Architect of global infrastructures for the next gen Intel server processors. ### Component Design Engineer @ Intel Corporation Jan 2012 – Jan 2014 | Folsom, California, United States In my role as a Component Design Engineer at Intel Corporation, I drove post-silicon validation of the Memory Controller Interface for Broadwell, the world's first 14nm product. I developed test plans for DDR3L and LPDDR3 technologies, ensuring comprehensive system validation coverage. Additionally, I played a key role in debugging failures in MC test-plan execution, ensuring a smooth silicon powering on process in the lab. ### Teaching Assistant @ University of Pennsylvania Jan 2012 – Jan 2012 | Philadelphia, Pennsylvania, United States Lead Teaching Assistant for the graduate level course in Digital Integrated Circuits and VLSI Fundamentals ### Research Assistant @ University of Pennsylvania Jan 2011 – Jan 2012 | Philadelphia, Pennsylvania, United States In my role as a Research Assistant at CERN and the University of Pennsylvania, I was responsible for designing and developing a Data Acquisition ASIC for the Silicon Tracker system at CERN. This involved working closely with the department to commission the ASIC and module readout design of silicon strip sensors for the ATLAS Detector System. Additionally, I conducted analog simulations of the designed module in Cadence to ensure optimal performance and functionality. ### MS in Electrical Engineering @ University of Pennsylvania Jan 2010 – Jan 2012 | Philadelphia, Pennsylvania, United States Area of Specialization: Computer Architecture and Digital VLSI ### Research Engineer @ Centre for Development of Telematics (C-DOT) Jan 2009 – Jan 2010 -Worked on developing and testing of a nationwide centralized security monitoring system of strategic importance to India ### Industrial Trainee @ Bharat Electronics Limited Jan 2007 – Jan 2007 Trained on the integration of ATM Switches for C4I-Command, Control, Communication Computer's Intelligence System designed to ease the burden of the command team in the ship and to strengthen the effectiveness of the decision making process in modern naval scenarios of the Indian Army. ### Student Intern @ Indian Institute of Information Technology, Allahabad, India Jan 2007 – Jan 2007 -Researched on the various techniques of Musculo-Skeletal Simulation ## Education ### Master of Science - MS in Electrical and Computer Engineering University of Pennsylvania ### Master of Business Administration - MBA in Business Administration and Management, General Santa Clara University Leavey School of Business ### Bachelor of Technology in Electronics and Communication Engineering National Institute of Technology, Tiruchirappalli ### All India Senior Secondary School Examination in Science Abu Dhabi Indian School (CBSE) ### High School in All India Secondary School Examination Ideal Indian School (CBSE) ## Contact & Social - LinkedIn: https://linkedin.com/in/sananda-ghosh --- Source: https://flows.cv/sananda JSON Resume: https://flows.cv/sananda/resume.json Last updated: 2026-04-05