# Sandeep Kasargod

> Builder: people, technology

Location: Dublin, California, United States
Profile: https://flows.cv/sandeepkasargod

Experienced technical leader with a demonstrated history of taking concepts to products, applying robust engineering rigor and developing breakthrough technologies. Seeking the next challenge.

## Work Experience
### Staff Engineer @ Rescale
Jan 2022 – Present

### Bootstrap + Sabbatical @ and now for something completely different
Jan 2021 – Present

### Senior Software Development Engineer @ Amazon Web Services (AWS)
Jan 2019 – Jan 2021 | Cupertino
AWS Elastic Block Store (EBS) client protocols: Network storage protocols that provide scalable, highly available and high performance persistent storage to EC2 instances. Migrating EBS traffic from storage from TCP/IP to NVMr for EC2, Ops, Nitro hardware.

### Technical Director SW Engg @ Vexata
Jan 2014 – Jan 2019 | San Francisco Bay Area
Ultra high performance enterprise grade storage array - 80GB/s, <100us
- Developed the core storage OS, High availability, Non disruptive updates, Application infrastructure, CLI. 
- Developed Ansible modules, Openstack Cinder driver, Docker storage plugins.
- Architecture and implementation of SW engg infrastructure and integration for Dev, FVT, QA
- Release management
- C++, Python, Bash. Familiar with Ethernet, NVMe, FiberChannel, PCIe SRIoV, Intel DPDK, lockless design, HW/SW interfaces

### Associate @ Sand Hill Angels
Jan 2012 – Jan 2016 | Palo Alto
Working with the SHA Screening committee and doing due diligence for prospective SHA investments.

### Sr. R&D Engineer @ Keysight Technologies
Jan 2006 – Jan 2014 | Massy, France; Santa Clara, CA
Developed the industry leading highest capacity RFIC simulation software, GoldenGate.
Xpedion was acquired by Agilent Technologies in 2006. Keysight was spun out from Agilent in 2014.
- GoldenGate dev lead for all frontend language parsing, optimization, PDK compatibility issues
- Distributed Monte Carlo simulation architecture, multi server as well as multi-process and multi-core parallel scaling and results processing.
- Implemented speed and capacity improvements, first 64bit port.
- Chair TSMC Model Interface subcommittee for Si2
- C++, Boost, Python, Perl

### Sr Software Engineer @ Xpedion Design Systems (acquired by Agilent Technologies)
Jan 2004 – Jan 2006 | Milpitas, CA; Limoges, France
A startup developing the highest capacity, transistor level RF-IC simulation and verification tool: GoldenGate.

### Research Asistant @ Dept. of Computational Molecular Biology & Bioinformatics, USC
Jan 2003 – Jan 2004
Developing software for showcasing research in the Computational Molecular Biology department at USC. - Java/JNI simulators for last common ancestor modeling, web application for common document sharing/restriction.
- Resident consultant helping out PhD students, faculty  and PostDocs with software development.
- Java, C++, PHP

### Engineer @ MobileSys Inc (merged with mBlox)
Jan 2000 – Jan 2002
Mobilesys was a startup developing enterprise middleware to deliver text messages to wireless carriers and devices globally. MobileSys is now a part of M-Blox. Implemented high throughput wireless messaging protocols for the XML based store and forward messaging engine. Developed robust web services for 24/7 messaging middleware and remote management console applications for the Network Operations Center.
- Mobile messaging protocols, XML, MySQL
- C, Java, Perl

### President @ Fair Oaks Toastmasters
Jan 2001 – Jan 2002 | Sunnyvale, CA
Instrumental in the formation of the club, also held office as VP Education. Lead membership recruitment drives and as President shepherded it through to ultimately obtain the formal charter as club #7528, District 4 (Northern California).

### Development Engineer @ Mentor Graphics Inc.
Jan 2000 – Jan 2000
Mentor Graphics acquired Escalade corporation in 2000. At Mentor I was responsible for the transition and integration / technology migration between Escalade’s ‘DesignBook’ tools and Mentor Graphics’ ‘Renoir’ tools.

### Member of Technical Staff @ Escalade Corp. (acquired by Mentor Graphics Inc.)
Jan 1997 – Jan 2000
Digital EDA startup. DesignBook, a high level design capture and validation framework - Responsible for the Hierarchical Finite State Machine/ Truth Table editors and a parameterizable library of drop-in components (ModuleWare). These tools generated synthesis optimized and simulation accurate Verilog/VHDL. Contributed to the Knowledge Extraction product - HDL to high level semantic representation extraction.


## Education
### M.S. in Electrical Engineering
University of Southern California

### B. Tech in Electrical Engineering
Indian Institute of Technology, Bombay


## Contact & Social
- LinkedIn: https://linkedin.com/in/sandeep-kasargod-b3b258

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Source: https://flows.cv/sandeepkasargod
JSON Resume: https://flows.cv/sandeepkasargod/resume.json
Last updated: 2026-04-12