Lead Physical Design work, Implementation. STA.

Led the CPU Implementation team in delivering 3+GHz Multithreaded, Out of Order server processor.

Designed and implemented DDR4 complex. Involved in complete design of the clock tree, DLLcell design and data and clock skew tuning.

Silicon proven in cutting edge technology.

Led a team of engineers in development of complete standard cell library for the processor in 16ff+ technology. Involved in the PG grid definition for CPU & SOC for optimal IR drop performance and routing. Defined clock grid for the CPU.

Reponsible for RegisterFiles, Multiport RegisterFiles, CAMS, I/Os and some IP.

Designed Multiport RegisterFiles, CAMS.

Closed timing on Scheduler block in CPU.

Helped in timing closure of other blocks.