I'm an engineering leader with 25+ years of experience delivering complex silicon — AI accelerators, deep-learning ASICs, and high-performance networking SoCs — with a focus on first-pass success.
Experience
2024 — Now
2024 — Now
Mountain View, CA
Owner of SoC pre-silicon verification, emulation, and co-simulation — from block-level through full-chip tape-out readiness.
Built a semantic retrieval system with optimized embeddings and a dynamic knowledge graph to index architecture specs, RTL, software models, and DV collateral at scale; used this infrastructure to automatically lint architecture documents, surface discrepancies across the architecture, software model, and RTL layers, and generate DV collateral and RTL from the unified knowledge base.
Integrated a Rust-based cycle-accurate model into RTL simulation and emulation via a custom IPC layer (named FIFOs, memory-mapped files), enabling hardware-software co-simulation and precise failure localization across the hierarchy.
Architected Bluespec-based Memory Replay stubs for cycle-by-cycle behavioral co-execution alongside RTL simulation or emulation — enabling large SoCs to be fully mapped to emulation platforms with bit-exact behavioral accuracy.
Established Bazel-based hermetic build and test infrastructure; led technical screening and hiring for pre-silicon, emulation, and simulation roles.
2021 — 2024
2021 — 2024
Santa Clara, CA
Built RTL design, verification, and automation organizations from the ground up; established and managed an offshore verification program that maintained quality while materially reducing cost.
Developed a sophisticated UVM constrained-random verification environment with translational sequences, DPI communication layers, and open-socket interfaces; enabled full software-stack execution within the RTL testbench for early architectural, performance, and power-efficiency analysis.
Delivered a transaction-accurate functional model enabling concurrent hardware-software co-development; authored a Python-based deep-learning topology generator and hardware mapper for comprehensive RTL and software test coverage.
Designed versatile coverage-driven verification environments spanning RTL unit-level simulation, SoC simulation, emulation, FPGA, and post-silicon validation — enabling chip bring-up in under two weeks through portable pre-silicon testing strategies.
2017 — 2021
Santa Clara, CA
Led functional verification of the Tensor Processor Core, Convolution Engine, and Internal Memory Banks for Intel Nervana's deep-learning accelerator — design featured at Hot Chips Conference.
Bridged a QEMU User Mode driver with the UVM SystemVerilog testbench to execute the complete software stack within RTL simulation; also constructed a post-silicon issue replication environment for rapid triage.
Co-architected the C++ functional reference model; pioneered a cost-based neural-network distribution optimizer and microcode generator in Python.
Led the post-silicon bring-up team as primary technical resource for hardware and software debug through chip validation.
2015 — 2017
2015 — 2017
Santa Clara, CA
Led functional verification of the Synchronous Hub driving 8K display pipelines.
Modernized the verification infrastructure by migrating to UVM.
Analyzed and improved display IP performance.
2012 — 2015
Milpitas, CA
Verified PCIe, MAC, and PHY subsystems for 2.5/5/10GBaseT products.
Led offshore verification team responsible for PCIe and Scatter Gather DMA Engine.
Managed low-power multi power domain simulations (UPF) and architected versatile verification environments.
Collaborated with cross-functional teams for NBaseT PHY integration.
Education
Villanova University
MS
Drexel University