# Shahriar Seyedhosseini

> I Argue With Simulators for a Living

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/shahriar

I'm an engineering leader with 25+ years of experience delivering complex silicon — AI accelerators, deep-learning ASICs, and high-performance networking SoCs — with a focus on first-pass success. My work spans RTL design, SoC-level pre-silicon verification, emulation, formal methods, cycle-accurate modeling, and hardware-software co-simulation.
What I find myself doing more and more: applying AI to close the chip development loop. At MatX, I built infrastructure that uses semantic retrieval, knowledge graphs, and a learning database to query architecture documents at scale — automatically linting them, surfacing discrepancies across architecture specs, software models, and RTL, and generating DV collateral and RTL directly from that analysis.
Outside of work, I'm building Archon — an AI-native chip development platform with an ambitious scope: replacing traditional simulators with agentic verification pipelines today, and progressively taking over synthesis closure and physical design flows as the platform matures. It orchestrates a full hierarchy of specialized agents — formal provers (Lean, Z3), coverage analyzers, RTL generators, UVM testbench synthesizers, and synthesis feedback loops — all iterating against a dynamic knowledge graph and a mistake-prevention learning engine, converging on verified, tape-out-ready implementations with minimal human-in-the-loop overhead.
I entered Archon in the ISQED 2026 Agentic AI Design Verification Challenge — a global open competition organized by PilotCrew.AI, UC Davis, and UC San Diego, where agents competed on real hardware IPs evaluated for coverage depth, automation sophistication, and engineering rigor — and placed 3rd among 35 participants, all seasoned experts spanning both design verification and AI.
I'm particularly interested in:
AI-driven hardware design and verification automation
Scalable SoC development infrastructure
Hardware-software co-design at system scale
If you're working at the intersection of AI and chip design, or thinking about how agentic systems can transform silicon development, I'd like to connect.

## Work Experience
### Silicon Swiss Army Knife @ MatX
Jan 2024 – Present | Mountain View, CA
Owner of SoC pre-silicon verification, emulation, and co-simulation — from block-level through full-chip tape-out readiness.
Built a semantic retrieval system with optimized embeddings and a dynamic knowledge graph to index architecture specs, RTL, software models, and DV collateral at scale; used this infrastructure to automatically lint architecture documents, surface discrepancies across the architecture, software model, and RTL layers, and generate DV collateral and RTL from the unified knowledge base.
Integrated a Rust-based cycle-accurate model into RTL simulation and emulation via a custom IPC layer (named FIFOs, memory-mapped files), enabling hardware-software co-simulation and precise failure localization across the hierarchy.
Architected Bluespec-based Memory Replay stubs for cycle-by-cycle behavioral co-execution alongside RTL simulation or emulation — enabling large SoCs to be fully mapped to emulation platforms with bit-exact behavioral accuracy.
Established Bazel-based hermetic build and test infrastructure; led technical screening and hiring for pre-silicon, emulation, and simulation roles.

### Director Of Engineering @ Analog Inference
Jan 2021 – Jan 2024 | Santa Clara, CA
Built RTL design, verification, and automation organizations from the ground up; established and managed an offshore verification program that maintained quality while materially reducing cost.
Developed a sophisticated UVM constrained-random verification environment with translational sequences, DPI communication layers, and open-socket interfaces; enabled full software-stack execution within the RTL testbench for early architectural, performance, and power-efficiency analysis.
Delivered a transaction-accurate functional model enabling concurrent hardware-software co-development; authored a Python-based deep-learning topology generator and hardware mapper for comprehensive RTL and software test coverage.
Designed versatile coverage-driven verification environments spanning RTL unit-level simulation, SoC simulation, emulation, FPGA, and post-silicon validation — enabling chip bring-up in under two weeks through portable pre-silicon testing strategies.

### Principal Deep Learning Engineering Manager @ Intel Corporation
Jan 2017 – Jan 2021 | Santa Clara, CA
Led functional verification of the Tensor Processor Core, Convolution Engine, and Internal Memory Banks for Intel Nervana's deep-learning accelerator — design featured at Hot Chips Conference.
Bridged a QEMU User Mode driver with the UVM SystemVerilog testbench to execute the complete software stack within RTL simulation; also constructed a post-silicon issue replication environment for rapid triage.
Co-architected the C++ functional reference model; pioneered a cost-based neural-network distribution optimizer and microcode generator in Python.
Led the post-silicon bring-up team as primary technical resource for hardware and software debug through chip validation.

### Senior Member of the Technical Staff @ NVIDIA
Jan 2015 – Jan 2017 | Santa Clara, CA
Led functional verification of the Synchronous Hub driving 8K display pipelines.
Modernized the verification infrastructure by migrating to UVM.
Analyzed and improved display IP performance.

### Principal Member of the Technical Staff @ Aquantia
Jan 2012 – Jan 2015 | Milpitas, CA
Verified PCIe, MAC, and PHY subsystems for 2.5/5/10GBaseT products.
Led offshore verification team responsible for PCIe and Scatter Gather DMA Engine.
Managed low-power multi power domain simulations (UPF) and architected versatile verification environments.
Collaborated with cross-functional teams for NBaseT PHY integration.

### Design Verification Manager @ Chelsio Communications
Jan 2007 – Jan 2012 | Sunnyvale, CA
Managed DV team covering PHY, PCIe SR-IOV, Scatter Gather Engine, FCoE, and RDMA verification.
Developed a comprehensive verification environment for SR-IOV-enabled PCIe and Scatter Gather Engine in SystemVerilog.
Developed CPU, host driver, and host memory behavioral models in SystemVerilog to achieve comprehensive functional coverage closure.

### Project Manager @ Electrolux
Jan 2006 – Jan 2007
Managed vendor relationships and supply chain coordination across a multi-vendor hardware program; 
drove cost reduction through strategic parts selection and testing.

### Co-Founder @ SPTEK LLC
Jan 2005 – Jan 2006 | Downingtown, PA
Founded an early IoT startup building wireless sensor network infrastructure for automated home climate control — independently controlling room temperatures through intelligent vent actuation.

### Member Of Technical Staff @ Unisys
Jan 1999 – Jan 2006 | Malvern, PA
Designed and verified PCI targets, bus masters, LZW decompressors, and memory controllers in VHDL and Verilog targeting Xilinx FPGAs.
Contributed across ASIC design, verification, and hardware prototyping on multiple programs.
Awarded Patent US7071854B1 — Hardware-Implemented LZW Data Decompression (granted 2006).


## Education
### MS in Electrical Engineering
Villanova University

### BS in Electrical Engineering
Drexel University


## Contact & Social
- LinkedIn: https://linkedin.com/in/shahriar1359

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Source: https://flows.cv/shahriar
JSON Resume: https://flows.cv/shahriar/resume.json
Last updated: 2026-04-13