DDR RTL Design Manager

• Managed a team of 19 engineers to develop RTL design for a new server class DDR architecture, supporting IP

across 3 SOCs.

• Empowered the team to innovate and create scalable designs for server and high-end desktop versions with aggressive timelines.

• Collaborated with Architecture, Physical Design, Verification, Behavioral Modelling, and Firmware teams for

successful tape out and bring up.

• Lead methodology group to minimize waivers, build the IP correct by construction, refine processes and

encourage innovation with the latest tools, including AI, while aligning these efforts across the entire

organization.

• Served as tech lead for a team of 10 engineers across 3 geos to deliver a successful SerDes PHY with PCIe Gen5 capability and going to 40GBPs data-rate.

• Owned quality metrics and STA for both IPs.

• Delivered a SerDes spin off for multichip high-speed IO in record time of 8 months, successful bring up

and characterization

• Developed methodology for the RTL community to automate inter-block connectivity using synthesizable

System-Verilog interfaces. Established processes for writing register blocks and delivering external

customer-facing register documentation.

Lead RTL design and infrastructure, including static timing analysis for SerDes PHY across the latest slew of AMD products.

Lead the verification efforts for testing the functional and mixed signal aspects of SerDes PHY for various protocols including PCIe,SATA,USB,SGMII and TMDP/DPRX across several programs and technologies using UVM based verification suite.

Verified DFT/Characterization features for SerDes PHY , including boundary scan, ATPG scan setup, Scan Dump, Loopback for BER testing, Characterization of PLL Jitter, DLL monotonicity, Programming registers through JTAG.

Performed Low power simulations (VCS-NLP or MVSIM) on all the SerDes PHYs.

Performed XA based simulations to verify the analog-digital interface and perform closed loop analysis of mixed signal designs.

Developed testbenches that could test the functional equivalency between RTL and Gate-Level models of the SerDes PHY designs and automated the integration of gate-level models into the test flow.

Developed several automation scripts(perl and cshell) to make the verification flow more efficient, that included automation of test regressions, parsing of ATPG logs through perl to extract scan chain stitch-up, parsing of verilog RTL to auto populate some parts of testbench etc.

Evaluated tools such as ZOIX (fault simulation tool) and VCS-NLP(low power sims) to be integrated into the verification flow.

o Trained over 100 professionals, including cross-departmental engineers in digital logic design and circuits, FPGA programming with VHDL.

o Developed VHDL lab exercises,support documentation software tutorials and maintained web resources.

o Evaluated as top 1% of instructors consecutively for two semesters.