# Shalini S. > Engineering Manager | exAMD | KU Alumni Location: San Jose, California, United States Profile: https://flows.cv/shalinis ## Work Experience ### ASIC & FPGA Eng Asc Mgr @ Lockheed Martin Jan 2025 – Present ### RTL Design Manager @ AMD Jan 2021 – Jan 2025 | San Francisco Bay Area DDR RTL Design Manager • Managed a team of 19 engineers to develop RTL design for a new server class DDR architecture, supporting IP across 3 SOCs. • Empowered the team to innovate and create scalable designs for server and high-end desktop versions with aggressive timelines. • Collaborated with Architecture, Physical Design, Verification, Behavioral Modelling, and Firmware teams for successful tape out and bring up. • Lead methodology group to minimize waivers, build the IP correct by construction, refine processes and encourage innovation with the latest tools, including AI, while aligning these efforts across the entire organization. ### SMTS Design Engineer @ AMD Jan 2017 – Jan 2021 | Santa Clara • Served as tech lead for a team of 10 engineers across 3 geos to deliver a successful SerDes PHY with PCIe Gen5 capability and going to 40GBPs data-rate. • Owned quality metrics and STA for both IPs. • Delivered a SerDes spin off for multichip high-speed IO in record time of 8 months, successful bring up and characterization • Developed methodology for the RTL community to automate inter-block connectivity using synthesizable System-Verilog interfaces. Established processes for writing register blocks and delivering external customer-facing register documentation. ### MTS Design Engineer @ Advanced Micro Devices Jan 2008 – Jan 2017 Lead RTL design and infrastructure, including static timing analysis for SerDes PHY across the latest slew of AMD products. Lead the verification efforts for testing the functional and mixed signal aspects of SerDes PHY for various protocols including PCIe,SATA,USB,SGMII and TMDP/DPRX across several programs and technologies using UVM based verification suite. Verified DFT/Characterization features for SerDes PHY , including boundary scan, ATPG scan setup, Scan Dump, Loopback for BER testing, Characterization of PLL Jitter, DLL monotonicity, Programming registers through JTAG. Performed Low power simulations (VCS-NLP or MVSIM) on all the SerDes PHYs. Performed XA based simulations to verify the analog-digital interface and perform closed loop analysis of mixed signal designs. Developed testbenches that could test the functional equivalency between RTL and Gate-Level models of the SerDes PHY designs and automated the integration of gate-level models into the test flow. Developed several automation scripts(perl and cshell) to make the verification flow more efficient, that included automation of test regressions, parsing of ATPG logs through perl to extract scan chain stitch-up, parsing of verilog RTL to auto populate some parts of testbench etc. Evaluated tools such as ZOIX (fault simulation tool) and VCS-NLP(low power sims) to be integrated into the verification flow. ### Adjunct Instructor for Digital Logic Design @ University of Kansas Jan 2007 – Jan 2008 o Trained over 100 professionals, including cross-departmental engineers in digital logic design and circuits, FPGA programming with VHDL. o Developed VHDL lab exercises,support documentation software tutorials and maintained web resources. o Evaluated as top 1% of instructors consecutively for two semesters. ### Network Planner @ Sprint Nextel Jan 2006 – Jan 2007 o Planned, Designed, and maintained network components to support the communication on CDMA wireless switches. o Prepared annual capacity plans for mid-west markets to ensure 0% dropping of calls. o Trained in deployment of Nortel CDMA based equipment(1XRTT,1XEVDO) and WiMax technology. ### Graduate Research Assistant @ University of Kansas Jan 2004 – Jan 2006 o Developed an efficient active antenna system that surpassed existing designs. Resulting in over 60% reduction in cost and 75% in footprint. o Designed single and double stage amplifiers for active antenna system using GaAs technology , fabricated, tested and troubleshooted prototypes. o Worked with cross-departmental teams to integrate radar and antenna systems into UAVs, tested for EMI/EMC compatibility and feasibility of operation in harsh environments. o Provided detailed documentation and technical presentations to research groups to procure NSF funding. ## Education ### MS in Electrical Engineering The University of Kansas ## Contact & Social - LinkedIn: https://linkedin.com/in/shalinisodagam --- Source: https://flows.cv/shalinis JSON Resume: https://flows.cv/shalinis/resume.json Last updated: 2026-04-13