# Shanmugam Kailasam > Splunk backend engineering Location: San Francisco Bay Area, United States Profile: https://flows.cv/shanmugam My interests include technical leadership and developing highly scalable and performant systems at the interplay of systems and business logic. My career journey has been building C/C++ based software across spectrum of disciplines that includes SaaS and Distributed Systems, Data Analytics Backend, Systems-Storage & Networking stack across Firmware, Linux/Solaris Kernel and User space layers. Over years, I've been a technical lead and developer for products and solutions in the areas of Data Analytics, Content optimization and distribution for large scale networking applications, High-Availability Storage, Linux/Solaris kernel and applications, Data De-duplication Encoding and Decoding, and Firmware for x86 & IO subsystem protocols. ## Work Experience ### Principal Software Engineer @ Splunk Jan 2019 – Present | San Francisco Bay Area Splunk core data platform, C++. ### MTS - Principal Engineer @ Riverbed Technology Jan 2017 – Jan 2019 | San Francisco Bay Area Principal Engineer leading Indexing and Storage component of WAN accelerator. - Lead technical contact and represented Riverbed in discussions and partnerships in improving their WAN accelerator product-line by introducing NVME in storage tier and taking advantage of improved NVME read/write semantics. - Improvements and fixes to C++ based Indexing and Search (encompasses TCP/IP connection handling and mux/demux data segments over ingress/egress, Storage & Caching), Multithreading and Memory Management. - Lead effort to run WAN Accelerator as a container service on their SD-WAN appliance replacing KVM based virtual machine thus eliminating heavy Storage and Network penalties imposed by VMKernel IO layers. - Scaling content store and caching by decoupling Index tier into a scalable and replicated cluster for SaaS solution. ### Technical Lead, Storage products Development @ PMC-Sierra is now Microsemi Jan 2011 – Jan 2017 | Sunnyvale, USA Technical lead and coding storage stack for performant, fault-tolerant and scalable storage solutions. Key contributor in solving several problems related to Block Virtualization and handling fault-tolerance aspects of data, Caching, Performance and Scalability, high speed Metadata indexing and locking, RAID, Rebuilding, Backup, Migration, Snapshot, Erasure Coding, API design for Middleware features and Storage Management. Contributed in Linux/ESXi kernel and Application components for various key deliverables. (Continued my roles and responsibilities when PMC-Sierra was acquired and renamed to Microsemi Storage Solutions US INC) ### Principal Software Engineer, Network Virtualization @ Emulex Jan 2010 – Jan 2011 | Emulex Implemented and Delivered Solaris 11 Network stack drivers and IO acceleration for network boot protocol. Ensure correct functionality of the network interface under various scenarios of OS Virtualization (Hypervisor, Containers), QoS, VLAN, tunneling, link aggregation, classification and traffic routing etc., NUMA performance optimization, problem isolation and fixing though Dtrace and kernel debugging methods, Performance engineering and improvement. ### Technical Lead, Firmware Development @ Adaptec Jan 2003 – Jan 2010 Key contributor in areas encompassing various RAID system implementations, caching, replication, snapshot and fault-tolerance/mitigation methods. Involved in SDLC including conception, implementation and customer delivery. Understanding of file systems, storage architectures, data redundancy algorithms, Caching, Scalability and Performance, IO protocols and state machines, Linux kernel modules, configuration and management application. Implemented protected mode execution of SAS/SATA protocol stack library for boot and runtime execution. Implemented bringup for MIPs and ARM based SoCs and IO controllers, and handled changes for hardware/software interaction modules for offload engines such as XOR, DMA and Erasure Codes. Experience handling In-circuit emulators(ICE) to debug and solve tricky issues related to x86 execution states. Handled protocol analyzers to trace and analyze SCSI/SAS and SATA protocol level behaviors and solve issues. Continued my roles and responsibilities when Adaptec India was brought under HCL Technologies on July 22, 2008. ### Software Development Consultant @ Thales Rail Signalling Solutions Jan 2007 – Jan 2008 As a consulting engineer, implemented system software changes to upgrade the platform and core infrastructure software for Thales distributed Railway signaling systems, Canada during their major hardware and software refresh. Implemented several core x86 architecture specific functionalities to the platform infrastructure (Embedded OS) including memory mapping for PCI and IO peripherals for message IO communication channel, protected mode segmentation, process page protection using x86 paging mechanisms and task management. ### Firmware Developer - Intel Architecture and Server platforms @ Wipro-Intel Development Center Jan 2002 – Jan 2003 Developer during early stages of EFI server firmware. Had opportunity to work closely with architects at Intel involving through design discussion, coding, validating with automated test suites, parsing logs and isolating misbehaviors that would help narrow down bugs in hardware software interactions and malfunctions. I was specifically focusing on software modules handling x86 processor, PCI Bus, IO, ACPI power management and system information database related functionalities. Also helped bootstrap IXP network processor and network protocol stack. ### Senior Systems Software Engineer @ American Megatrends Jan 2000 – Jan 2002 | American Megatrends Inc. Implemented platform firmware code (BIOS) in x86 assembly for various chipsets and IO controllers on servers and workstation systems. Handled the full suite of platform bringup including - System Power-on state handling, memory controller initialization, PCI bus enumerations and resource assignment, system memory/address space setup, Interrupt routing through (legacy and APIC) controllers, boot loaders, system BIOS management, ACPI power management etc. Through several projects and out of interest, developed deep knowledge on x86 architecture, memory hierarchy, addressing and performance impacts around cache, protected mode and virtual addressing, IO (Bus architectures/Device IO transport and DMA) and system software interaction. Developed file system crawler, to perform block based snapshot and restore for NTFS, ext2 and FAT32 filesystems. ## Education ### Masters in Computer Applications in Computer Science Bharathiar University ### Applied Sciences in Computer Technology/Computer Systems Technology PSG College of Technology ## Contact & Social - LinkedIn: https://linkedin.com/in/shanmu --- Source: https://flows.cv/shanmugam JSON Resume: https://flows.cv/shanmugam/resume.json Last updated: 2026-04-12