# Shantanu Gupta

> On a career break

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/shantanu

Currently tinkering with VR @apple; previously heterogenous x86 CPUs and Windows @intel and @microsoft

## Work Experience
### Senior Software Engineer @ Apple
Jan 2023 – Jan 2026 | San Francisco Bay Area
Platform diagnostics for Vision products

### Senior Software Engineer @ Intel Corporation
Jan 2022 – Jan 2023 | Redmond, WA
Microsoft Windows OS co-engineering for Meteorlake and Lunarlake platforms

Hardware Guided Scheduling, VVC decode, SoundWire enablement, PresentAt, perf & power tracking

### Software Engineer @ Microsoft
Jan 2019 – Jan 2022 | Redmond, WA
Display Kernel, SiGMa (Silicon, Graphics & Media)

Shipped IddCx 1.4->1.9 (Optimizing RDP, xbox cloud, IoT display presentation infrastructure), DisplayPort WDDM APIs and supporting HLK test suite, DP MST and USB4 topology mapping library, drove discussions with industry partners (Nvidia, Intel, Qualcomm, AMD) on DP strategy, represented Microsoft interests in VESA task group for link and test implementation.

### Software Engineering Intern @ Microsoft
Jan 2018 – Jan 2018 | Redmond, WA
Indirect adapter support in VR display subsystem - SiGMa, COSINE

### Software Engineering Intern @ Markforged
Jan 2018 – Jan 2018 | Cambridge, MA
Fast medial axis transform approximation for 2D polygons using constrained delaunay triangulation and steiner points

### Software Engineering Intern @ Microsoft
Jan 2017 – Jan 2017 | Cambridge, MA
Rapid prototyping and development - NERD, AI & Research

### Full Stack Intern @ Sourcegraph
Jan 2016 – Jan 2016 | San Francisco Bay Area
Developed and Integrated better code intelligence with existing development environments

• Wrote a recursive descent parser for GitHub’s DOM to inject code intelligence
• Wrote a Microsoft LSP compliant language server for CSS, SCSS and SASS

### Software Engineering Intern @ Palo Alto Networks
Jan 2016 – Jan 2016 | San Francisco Bay Area
Worked on PAN-OS 8.x and PA-5200 in Dataplane Platform Group

• Wrote linux userspace device driver for PMBus devices with SWIG bindings
• Modified system init to cache FPGA’s DDR tuning param, shaving minutes off boot-time.


## Education
### Bachelor of Science - BS in Computer Science
Drexel University
Jan 2015 – Jan 2019


## Contact & Social
- LinkedIn: https://linkedin.com/in/zeusk
- GitHub: http://www.github.com/zeusk

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Source: https://flows.cv/shantanu
JSON Resume: https://flows.cv/shantanu/resume.json
Last updated: 2026-03-22