Computer Architect with experience in delivering architecture models for AMBA CV processors, Performance Optimization to accelerate state of the art Transformer networks and translating the findings into hardware specifications as needed.

Experience

Ambarella IncSoftware Architecture Engineer

2018 — Now

San Francisco Bay Area

Performance optimization for Edge AI accelerators

AppleIntern, CPU Design team

2017 — 2017

Austin, Texas Area

NVIDIAASIC Engineer

2014 — 2016

Hyderabad Area, India

Verification of UART IP:

* Enhanced the UART Bus Functional Model to support the verification of new design features

* Developed directed and random test case scenarios for the functional verification of UART IP

* Analysed and reviewed Code and Functional Coverage reports to review coverage holes

* Executed the FPGA Emulation and Silicon Validation of UART IP for Tegra Parker processor

* Performance analysis to ensure Si meets the architecture supported baud rates and error tolerance

System Level Verification:

* Verified connectivity and functionality of the LSIO peripherals (UART/PWM/TACH) at SOC level for next generation Tegra processor

IGCARSummer Intern

2012 — 2012

Kalpakkam,India

Remote Field Eddy Current Testing (RFECT) for defect detection in steel tubes

Mentored by Dr.BPC Rao

* Extracted data from remote field eddy current sensors using high end ADCs

* Implemented lock-in amplifier functionality on the sensor data for defect detection in steel tubes

* Designed UI for acquiring and testing data from remote field eddy current sensor array

Tools Used : LabView

Education

Texas A&M University

Master of Science (M.S.)

Birla Institute of Technology and Science, Pilani

Experience

Education

Master of Science (M.S.)

B.E.(Hons)