# Shrinivasan Jaganathan

> Analog, Mixed Signal, RF IC Design Leader

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/shrinivasan

•	20+ years of industry experience with a passion of innovation and excellence in product development
       - Experience in managing remote cross-functional teams and delivering excellent results.
       - Managed the entire product cycle for several products starting from definition/conception  phase all the way to release of the product to market.
       - Proven track record of developing highly successful high performance products including several best-in-class ICs  in RF signal-chain for wireless infrastructure applications.
•	Drove the strategy for product development in the RF IC product group at TI. I have developed a good understanding of requirements of customers in different regions of the world and the need to define the product appropriately.
•	Demonstrated improved product quality by improving the design methodology through implementation of best design and layout practices and by improving the final test quality by working closely with the characterization and test engineers.
•	Deep technical understanding and hands-on design experience in RF, analog and mixed-signal ICs and system concepts - Mixers, modulators and demodulators, tuned amplifiers and distributed amplifiers, PLLs, data-converters, Band gap references, bias blocks, temperature sensors, feedback circuits, stability, signal integrity, power supply rejection, high linearity and low noise design, RF System and link budget analysis,  RF and microwave power amplifiers.
•	Strong theoretical understanding of semiconductor device physics in both silicon as well as III-V technologies.

## Work Experience
### Senior Director of Engineering @ Infinera
Jan 2021 – Present | Sunnyvale, California, United States

### Senior Director Of Engineering @ Empower Semiconductor
Jan 2015 – Jan 2021 | Fremont

### Design Engineering Director @ Cadence Design Systems
Jan 2013 – Jan 2015 | San Jose, CA

### Senior Design Manager, High Speed Interface IP @ Cosmic Circuits (Acquired by Cadence Design Systems,  May 2013)
Jan 2012 – Jan 2013 | Bangalore, India

### Design Manager, Industrial Interface @ Texas Instruments
Jan 2010 – Jan 2012

### RF Design Manager @ Texas Instruments
Jan 2002 – Jan 2010

### Design Engineer @ GTRAN
Jan 2000 – Jan 2002

### Graduate Student @ UC Santa Barbara
Jan 1996 – Jan 2000

### B. Tech. EE @ Indian Institute of Technology, Bombay
Jan 1989 – Jan 1993

### Student @ Kendriya Vidyalaya
Jan 1982 – Jan 1989


## Education
### PhD in Electrical Engineering
UC Santa Barbara

### Resrach Scholar in working toward a PhD in Physics, Solid State Electronics, Optical Electronics, Coursework in Physics
Tata Institute of Fundamental Research (TIFR)

### B. Tech. in Electrical Engineering
Indian Institute of Technology, Bombay

### High School/Secondary Diplomas and Certificates
Kendriya Vidyalaya, Indore

### Indian Institute of Technology, Bombay


## Contact & Social
- LinkedIn: https://linkedin.com/in/shrinivasan-jaganathan-79b6145

---
Source: https://flows.cv/shrinivasan
JSON Resume: https://flows.cv/shrinivasan/resume.json
Last updated: 2026-04-13