# sivakumar yagnamurthy > Product Design Leader | High-Performance Electronics, Mechanical & Systems Location: San Jose, California, United States Profile: https://flows.cv/sivakumaryagnamurthy Engineering leader with 13+ years of industry experience in developing electronic chips, modules, and mission-critical hardware systems, spanning consumer electronics and High-Performance Computing (HPC) applications. Proven success as a manager with experience leading and mentoring engineers, driving technical vision, and leading complex, cross-functional programs from concept to high-volume production (HVM). Strong record in influencing architecture and optimizing thermo-mechanical solutions at the chip-to-enclosure level. ## Work Experience ### Product Design FEA @ Apple Jan 2021 – Present • Lead a team of mechanical FEA engineers for the integration of Apple silicon into Mac and server products. • Drive key package and system design trade-offs to meet stringent mechanical, thermal, reliability and other targets. • Lead complex FEA-based simulations at chip, module and system-level; predict long-term performance under extreme operating conditions. ### Product Design Lead @ Intel Corporation Jan 2018 – Jan 2021 | Chandler, AZ • Mechanical Design Lead for high-volume Data Center server components with over 20 Million units shipped. • Owned architecture definition, detailed tolerance analysis, and final drawing release for critical components, ensuring adherence to strict quality requirements. • Performed extensive FEA and led physical testing (shock, vibration, thermal cycling) to validate designs and drive parts quality with manufacturing vendors. ### IC Packaging (FEA and Testing) @ Intel Corporation Jan 2013 – Jan 2018 | Chandler, AZ • Led thermo-mechanical FEA and validation testing, guiding package architecture, material selection, and predicting reliability performance for high-performance chips. • Supervised and mentored junior engineers while defining, executing, and validating advanced reliability testing (shock, drop, TC, Vibe). Hands-on expert in structural/thermal characterization using Instron, DIC, accelerometers, etc. • Partnered with global OSATs and Intel factories to execute qualification testing, solve field issues, and ensure a robust ramp into high-volume manufacturing (HVM). ### Research Assistant @ University of Illinois at Urbana-Champaign Jan 2007 – Jan 2013 | Urbana-Champaign Area • Developed experimental techniques to characterize mechanical and piezo-electric material properties. • Perform failure analysis using advanced techniques such as SEM, AFM, FIB, optical microscopes. ### Failure Analysis Engineer @ Seagate Technology Jan 2012 – Jan 2012 | Minnesota, United States • Measured the mechanical damage on magnetic heads using tools such as AFM, TEM and nano Auger. • Correlated the media disk defect geometry to electrical degradation of the computer hard drives. ### Technology Consultant @ PricewaterhouseCoopers India Jan 2006 – Jan 2007 | Bangalore ### Summer Internship @ Indian Space Research Organisation Jan 2005 – Jan 2005 | Sriharikota • Experimentally measured acoustic loads on a scaled down spacecraft model due to its exhaust jet. • Developed a computer code to model acoustic loads generated to match the experimental data. ## Education ### PhD in Aerospace Engineering University of Illinois Urbana-Champaign Jan 2009 – Jan 2013 ### M.S. in Aerospace Engineering University of Illinois Urbana-Champaign Jan 2007 – Jan 2009 ### B.S. in Aerospace Engineering Indian Institute of Technology, Madras Jan 2002 – Jan 2006 ## Contact & Social - LinkedIn: https://www.linkedin.com/in/sivakumar-yagnamurthy-33501516 --- Source: https://flows.cv/sivakumaryagnamurthy JSON Resume: https://flows.cv/sivakumaryagnamurthy/resume.json Last updated: 2026-04-07