# Suyog Prakash Tulapurkar

> Principal Engineer @ Nvidia | Functional Safety | GenAI

Location: San Jose, California, United States
Profile: https://flows.cv/suyog

NVIDIA:- Functional Safety Management, Software Safety and Security Architecture

CADENCE DESIGN SYSTEM: - Senior Functional Safety Engineer for Cadence/Tensilica SW products used in safety critical applications. Responsible for ISO 26262 safety plan implementation, including code review, static analysis (MISRA) and verification for Tensilica vision SW libraries and toolchain.

TATA CONSULTANCY SERVICES: - Embedded Software Developer for a CMMI level 5 Company providing firmware solutions to major Automotive, Medical, Networking and other companies. Worked in the field of Safety-Critical embedded firmware development. Good understanding of various industry standards like ISO 26262, IEC 61508, IEC 62304, MISRA and C11.

Skills:-
Programming Languages: C, C++, Python, Shell
MICROCONTROLLER Architecture: - Intel and ARM
Operating Systems: Windows, Linux/UNIX
Tools: gcc/gdb, Compilers and IDEs (MPLAB, PSoC, E2 Studio, Xtensa Explorer), LINUX Device Drivers, Eclipse, Bootloader/ASIC Development 
Hardware and Protocols: USB, Bluetooth, CAN, SPI, I2C, UART, RS232, ADC, Modbus, UDS, TCP/IP, UDP, DNS, Renseas and Microchip Micro-Controllers, Signal Oscillators
Configuration and Requirement Management: Git, Jama

## Work Experience
### Principal Software Engineer @ NVIDIA
Jan 2026 – Present | San Jose, CA
Functional Safety: ISO 26262, Safety Architecture, Safety Analysis, FuSa, Verification
GenAI: LLM orchestration, RAGs, Langchain, LLM Safety
Automation: Python, APIs, CI/CD, Docker

### Senior Software Safety Engineer @ NVIDIA
Jan 2022 – Jan 2026 | San Jose, CA
 Working as a Functional Safety Architect for Nvidia Tegra boot software.
 Responsible for safety planning (safety plan, verification plan), safety architecture and overall functional safety progress.
 Applying GenAI (LLMs, RAG Pipelines) to functional safety and security and studying its effectiveness.
 Functional Safety Management: - Safety Requirements, ASPICE, ISO26262, ISO21434
 Software Safety and Security Architecture: - FMEA, Safety Architecture, Threat Analysis
 GenAI: - LLM CI/CD Pipelines, RAGs, Semantic similarity analysis, NLP, LangChain

### Sr. Principal Test Engineer @ Cadence Design Systems
Jan 2020 – Jan 2022 | San Jose, California, United States
 Functional Safety Management for Cadence/Tensilica IP Software used for Safety Critical applications: - ISO 26262, Automotive Software, Engineering Management.
 Lead a team of safety engineers to verify/certify new versions of Cadence/Tensilica IP Vision Software libraries and XT-CLANG compiler toolchain to ISO 26262 ASIL D: - QA, Engineering Management, Functional Safety
 Worked to create and certify STL (Software Test Library) Safety Mechanism for Tensilica HW IP: - C, Assembly, HW Fault coverage, Functional Safety.
 Worked with OEMs and Tier-I automotive customers and certification bodies like TUV-SUD and SGS-TUV Saar

### Principal Test Engineer @ Cadence Design Systems
Jan 2017 – Jan 2020 | San Jose, California, United States
 Successfully completed ISO 26262 ASIL D certification if Cadence/Tensilica IP Vision Software libraries and XT-CLANG compiler toolchain used in Safety Critical applications: - ISO 26262 Compliance, Functional Safety, Automotive Software.
 Functional Safety Engineer for Cadence/Design IP Software products consisting of bare metal software drivers for USB, PCIe and other IPs: - C, Device Drivers (USB, PCIe, I2C), Unit Testing, Embedded Software.
 Code review, Static Analysis (MISRA), code coverage and verification for ISO 26262 compliant Vision Software library and low-level libraries (XTOS, HAL, iDMA): - C/C++, Unit Testing, Integration Testing, Embedded Software, Tensilica processors.
 Automation of safety work products creation and review. Work Products include Safety Plan, Software Requirements, Test Scripts, verification reports: - Python
 Good understanding of Hardware Functional Safety and performing Safety Analysis (FMEDA) on hardware components: - HW Safety Analysis, FMEA, FMEDA.

### Information Technology Analyst @ Tata Consultancy Services
Jan 2015 – Jan 2015 | Pune Area, India
	Designed and developed embedded diagnostic software based on CAN network protocol for vehicle diagnostics.
	Implemented various automotive software Safety standards such as ISO 26262 and MISRA-C for next generation ECU firmware development.

### Embedded System Engineer @ Tata Consultancy Services
Jan 2010 – Jan 2014 | Pune Area, India
	Developed firmware in C/C++ to implement the Vehicle Battery Management System ECU of Hybrid and Electric Vehicles.
	Implemented driver and system level embedded communication protocols (e.g. CAN, SPI, I2C, UART) for Renesas and Microchip microcontrollers using Embedded C.

### Software Engineer (consultant) @ Nissan Motor Corporation
Jan 2014 – Jan 2014 | Kanagawa, Japan
	Involved in ISO 26262 compliant next generation ECU design and development for NISSAN Electric Vehicles.
	Involved in testing the Embedded C/C++ firmware and data gathering along with defect tracking and analysis.


## Education
### Master’s Degree in Computer Science
Clemson University

### Bachelor’s Degree in Electrical and Electronics Engineering
Devi Ahilya Vishwavidyalaya


## Contact & Social
- LinkedIn: https://linkedin.com/in/sptulapurkar

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Source: https://flows.cv/suyog
JSON Resume: https://flows.cv/suyog/resume.json
Last updated: 2026-04-12