* Orchestrating the hardware-software handshake for massive-scale training and inference fleets, ensuring seamless integration between custom silicon and high-level software stacks.

* Designing the "safety net" for AI silicon: specializing in deterministic reset logic and hardware-software co-design to maintain high-uptime in mission-critical environments.

* Leading the end-to-end lifecycle of next-generation AI accelerators, from initial post-silicon bring-up to software updates for Superpod-scale deployments.