# Teju Khubchandani

> Senior Director, HPC @ Renesas | ex-Apple | ex-Google | Award-Winning Photographer (IPA 2025)

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/tejukhubchandani

With over 35 years of experience in silicon architecture, development, and management, I am a seasoned leader and innovator in the field of custom silicon solutions. I have shipped multiple products for Apple, Google, and other companies, ranging from smartphones, tablets, watches, and Macs to machine learning silicon, ISP ASICs, and network processors.

Currently, I am a Senior Director at Renesas Electronics, HPC Group.  My mission is to enable collaboration, encourage innovation, drive execution, and build consistency across teams and partners. I have a master's degree in electrical engineering from the University of Southern California, and I hold multiple patents in the area of configurable ICs. I am also an amateur radio enthusiast with a call sign of KJ6NLX.

Beyond my work in technology and silicon, I am an avid street photographer. In 2025, my work was recognized with 3rd Place in the Street Photography category as well as "Best of the show" at the International Photography Awards (IPA), one of the world’s most prestigious photography competitions.

## Work Experience
### Senior Director, High Performance Compute @ Renesas Electronics
Jan 2024 – Present | San Francisco Bay Area

### Director of Silicon Program Management @ Aeva, Inc
Jan 2021 – Jan 2023 | Mountain View, California, United States

### System Architecture & Silicon Platform Program Management Lead @ Google
Jan 2017 – Jan 2021 | Mountain View, California

### Engineering Manager, Custom Silicon Management @ Apple
Jan 2007 – Jan 2017 | Cupertino, CA
Shipped Product: Apple iPhones, Apple iPads, AppleWatch and Apple Macs

### ASIC Design Manager, Senior Member of Technical Staff @ Tabula, Inc.
Jan 2005 – Jan 2007 | Santa Clara, California
Design manager for digital core and digital verification.

### Manager, Product & Development (Consultant) @ Kawasaki LSI, Japan
Jan 2004 – Jan 2005
ASSP Architecture and design lead.  Re-ramped team's design tools/methodology.

### Manager, ASIC Design @ Andes Network
Jan 2000 – Jan 2004 | Mountain View
Architect and design key hashing FPGA.  Manage/Lead ASIC team.

### Senior ASIC Design Engineer @ VM Labs
Jan 1995 – Jan 2000 | Mountain View
Lead designer for display engine on VM's ASIC.

### ASIC Design Engineer @ NTG/3DO
Jan 1991 – Jan 1995 | Palo Alto
Lead designer for display engine in 3DO ASICs.


## Education
### MSEE in Electrical Engineering
University of Southern California
Jan 1989 – Jan 1990

### BSEE in Electrical Engineering
UC Irvine
Jan 1986 – Jan 1989


## Contact & Social
- LinkedIn: https://www.linkedin.com/in/mrteju
- Website: https://mrteju.myportfolio.com

---
Source: https://flows.cv/tejukhubchandani
JSON Resume: https://flows.cv/tejukhubchandani/resume.json
Last updated: 2026-04-07