▪ Designed and implemented C++ frameworks to control FPGA hardware workflows, including configuration, bitstream programming, runtime management, and automated validation sequences.
▪ Developed remote control capabilities for FPGA systems across distributed environments, enabling efficient remote testing and debugging.
▪ Optimized performance of the C++ control framework through multi-threaded execution and asynchronous task scheduling, improving throughput and reducing latency under load.
▪ Ported and validated existing tools across multiple CPU architectures (x86, ARM, and embedded platforms) to ensure cross-platform compatibility and consistent performance.
▪ Established GitLab CI/CD pipelines to automate regression testing, artifact management, and deployment of FPGA validation utilities.
▪ Integrated cross-team code-quality tools into CI/CD pipelines to enforce automated linting, testing, and static analysis before merges.
▪ Leveraged AI-assisted code optimization (LLM-based reviewers and static analysis insights) to enhance maintainability, performance, and code readability.
▪ Collaborated closely with Application Engineers (AEs) to reproduce and debug complex customer issues, bridging engineering and field operations for faster root-cause analysis and issue resolution.
Partnered with hardware and verification teams to streamline FPGA bring-up and unify software–hardware integration workflows.
