I'm helping improve the effcc Compiler to squeeze the most performance and efficiency out of our power-sipping spatial dataflow compute fabric --- targeting not just ML code (hello again #mlperftiny!) but also all the other code your embedded system needs to run (control, DSP, CV, etc.).

My role here involved compilers for custom accelerators, ML kernels for LLMs, simulators, and HW/algorithm co-design.

* Built an environment for rapid iterative co-design of a HW accelerator and the ML kernels that use it, for TinyML on FPGAs

• - https://github.com/google/CFU-Playground (fully open source)

• - Our team shipped a private and secure Human Presence Sensor subsystem in Chromebooks, using this framework to build a RISC-V extended with custom nano-TPU-like accelerator (implemented on FPGA using TFLite for Microcontrollers firmware).

* Member RISC-V Soft CPU & Custom Extensions Special Interest Group:

Composable custom extensions (https://lists.riscv.org/g/tech-announce/message/277)

* XLS High-level synthesis: https://github.com/google/xls

* ASIC tools for open source silicon: https://developers.google.com/silicon

Using Yosys, ABC, OpenROAD, OpenSTA

* Open source FPGA tools: https://f4pga.org/ (formerly SymbiFlow)

* Assisted the Google FHE (Fully-Homomorphic Encryption) team in the use of hardware synthesis and optimization in their open-source Transpiler flow. FHE allows processors to perform computations directly on encrypted data.

Used a SAT solving engine in a compiler back end to codegen, place, and "route" optimized parallel code for machine learning acceleration, and for linking multiple kernels together on the CGRA (coarse-grained reconfigurable array).

Advised the LLVM front end team regarding accurate translation of C semantics to Wave's internal graph representation.

Devised and implemented compiler workarounds for chip flaws as needed.

Member of the team specifying quantization for next-gen product.

Genus synthesis tool; architecture optimizations.