# Tim Callahan > Compilers, kernels, custom accelerators. Berkeley PhD. Location: Cupertino, California, United States Profile: https://flows.cv/timcallahan My interests include compilers, accelerators, ML/HW/SW co-optimization, edge ML, high-level synthesis, FPGAs, reconfigurable/spatial computing, heterogeneous computing, dataflow, and application-specific instruction sets. In my PhD work I built a compiler to automatically generate and use dynamically-loadable hardware accelerators for compute-intensive kernels, given only the original software description and profiling data as input. ## Work Experience ### Compiler Engineer @ Efficient Computer Jan 2025 – Present | San Francisco Bay Area I'm helping improve the effcc Compiler to squeeze the most performance and efficiency out of our power-sipping spatial dataflow compute fabric --- targeting not just ML code (hello again #mlperftiny!) but also all the other code your embedded system needs to run (control, DSP, CV, etc.). ### Compiler Engineer @ MatX Jan 2024 – Jan 2025 | Mountain View, CA My role here involved compilers for custom accelerators, ML kernels for LLMs, simulators, and HW/algorithm co-design. ### Staff Software Engineer @ Google Jan 2020 – Jan 2023 | Sunnyvale, CA * Built an environment for rapid iterative co-design of a HW accelerator and the ML kernels that use it, for TinyML on FPGAs -- https://github.com/google/CFU-Playground (fully open source) -- Our team shipped a private and secure Human Presence Sensor subsystem in Chromebooks, using this framework to build a RISC-V extended with custom nano-TPU-like accelerator (implemented on FPGA using TFLite for Microcontrollers firmware). * Member RISC-V Soft CPU & Custom Extensions Special Interest Group: Composable custom extensions (https://lists.riscv.org/g/tech-announce/message/277) * XLS High-level synthesis: https://github.com/google/xls * ASIC tools for open source silicon: https://developers.google.com/silicon Using Yosys, ABC, OpenROAD, OpenSTA * Open source FPGA tools: https://f4pga.org/ (formerly SymbiFlow) * Assisted the Google FHE (Fully-Homomorphic Encryption) team in the use of hardware synthesis and optimization in their open-source Transpiler flow. FHE allows processors to perform computations directly on encrypted data. ### Distinguished Member Of Technical Staff @ Wave Computing Jan 2017 – Jan 2019 | Campbell, CA Used a SAT solving engine in a compiler back end to codegen, place, and "route" optimized parallel code for machine learning acceleration, and for linking multiple kernels together on the CGRA (coarse-grained reconfigurable array). Advised the LLVM front end team regarding accurate translation of C semantics to Wave's internal graph representation. Devised and implemented compiler workarounds for chip flaws as needed. Member of the team specifying quantization for next-gen product. ### Senior Principal Software Engineer @ Cadence Design Systems Jan 2015 – Jan 2017 | San Jose, CA Genus synthesis tool; architecture optimizations. ### Senior Staff Engineer (Synthesis) @ Tabula Jan 2008 – Jan 2015 | Santa Clara, CA Compiling and optimizing for Tabula's novel pipelined heavily-multiplexed SpaceTime fabric. One specific area that I owned was the handling of Verilog/VHDL design memories through the synthesis flow: inference, optimizations, mapping to primitives on the SpaceTime fabric, ensuring correct scheduling precedence among multiple ports, and providing useful feedback to the user when their critical timing path included memory accesses. ### Systems Scientist @ Carnegie Mellon University Jan 2005 – Jan 2008 | Pittsburgh, PA Research in compiling C to low-power, asynchronous, application-specific hardware. ### Compiler Engineer @ SRC Computers Jan 2003 – Jan 2004 Added features and optimizations to the compilation flow from SRC's FPGA accelerator language (a subset of C) to Verilog, including software pipelining and OpenMP-style multithreading. ### Advanced Technology Group, Research Intern @ Synopsys Jan 1998 – Jan 1998 Nimble Compiler project: compiling C to hardware gates + software instructions, using technology and software from my PhD thesis work at Berkeley. ### Graduate Research Assistant @ ICSI - International Computer Science Institute Jan 1992 – Jan 1994 | Berkeley, CA Performed work on the Torrent vector microprocessor for machine learning / neural network applications including speech recognition, under the direction of Prof. John Wawrzynek and Krste Asanovic. ### Undergraduate Research Assistant @ Minnesota Supercomputing Institute Jan 1988 – Jan 1990 | Greater Minneapolis-St. Paul Area Authored protein structure analysis software; wrote interactive 3D visualization software for molecular dynamics simulations running on SGI workstations; ported energy minimization (protein folding) & molecular dynamics code from vector architectures (Cray) to shared-memory multiprocessors (SGI). ## Education ### Ph.D in M.S., Computer Science University of California, Berkeley ### Diploma in with Distinction, Computer Science University of Cambridge ### Bachelors in Summa Cum Laude, Electrical Engineering University of Minnesota ## Contact & Social - LinkedIn: https://linkedin.com/in/tim-callahan-fpga - Portfolio: https://developers.google.com/silicon --- Source: https://flows.cv/timcallahan JSON Resume: https://flows.cv/timcallahan/resume.json Last updated: 2026-04-10