# Tom Hergenrother

> ASIC/FPGA Design Engineer

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/tomhergenrother

## Work Experience
### ASIC/FPGA Design Engineer @ Ciena
Jan 2024 – Present

### Engineering Project Manager @ L3Harris Technologies
Jan 2018 – Jan 2024 | Santa Rosa, California, United States

### FPGA Design Engineer @ L3Harris Technologies
Jan 2018 – Jan 2018 | Santa Rosa, California, United States

### Director Program Management @ Enphase Energy
Jan 2017 – Jan 2018 | Petaluma, California, United States

### Director Engineering, Energy Storage @ Enphase Energy
Jan 2014 – Jan 2017

### Senior Manager, AQA @ Calix
Jan 2012 – Jan 2014 | Petaluma, California, United States

### Senior Manager, Hardware & Software Engineering @ Calix
Jan 2006 – Jan 2012 | Petaluma, California, United States

### Manager, ASIC Design @ Calix
Jan 1999 – Jan 2006 | Petaluma, California, United States

### ASIC Design Engineer @ Next Level Communications
Jan 1997 – Jan 1999 | Rohnert Park, California, United States

### ASIC Design Engineer @ DSC Communications
Jan 1992 – Jan 1997 | Petaluma, California, United States


## Contact & Social
- LinkedIn: https://linkedin.com/in/tomhergenrother

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Source: https://flows.cv/tomhergenrother
JSON Resume: https://flows.cv/tomhergenrother/resume.json
Last updated: 2026-04-13