Crafting an evidence-based roadmap to build the highest-performance CPU cores

Build MLIR-based compiler and prototype code transformations to co-optimize communication and

computation in distributed GPU workloads such as model-parallel training and inference for enormous ML models.

Develop analytical modeling tool for design space exploration and code optimization for efficient execution of linear algebra and machine learning workloads on a range of specialized hardware architectures.

Modified firmware (C) and created tools (Python) for debugging prototype embedded system hardware through a serial connection. Functionality included a simple command line interface, resource utilization monitoring, a GDB server, and a binary packet protocol with parity checks for accessing device memory and dumping debug messages.