• Develop and maintain data pipelines with ETL process from various sources and data types with Airflow, Python, AWS, and MySQL use for the inhouse AI/LLM model. This includes inferences, prompts, curation pipelines on text-based data.

• Optimize SQL queries/scripts to maintain the backend database.

• Lead the backend of Air Force projects by data modeling, improving the backend architecture and developing the API services.

• Optimize the performance of the backend services and improve capabilities with techniques such as Redis caching, streaming, indexing, and partitioning on data.

● Main workhorse behind the transfer of the highest volume BiCMOS technology from Linear Technology (currently Analog Devices) to Vanguard International Semiconductor Corporation (VIS).

● Successfully used machine learning models to tweak important implant parameters in order to help tune in the transfer technology (multiple Vt implants, NPN base implant, Spacers width, etc.). All were achieved within 1 single DOE each.

● Laid out PDV structures, scribeline devices, as well as setup and troubleshoot 700+ ET parameters on both sides to help the foundry transfer.

● Used a deep learning network architecture to help tune a new 100V low-side LDMOS for the best parameter optimization, giving 30% better Ron and 10V extra volts margin on the best known high side 100V NMOS available in the family. Final device achieved 250 Ron with 160V BVdss.

● Developed an in-house testing software system to help characterize the endurance as well as do burn-in at various temperature to determine the memory retention/activation energy for the in-house EEPROM cells.

● Done various characterizations for MOS, BJT, and many other passive devices, as well as troubleshooting issues with current devices such as fragility, leakages, and BVdss walk-in.

● Used TCAD simulation to determine splits to run for device optimization, as well as utilizing machine learning for fine-tuning to the best post-silicon value with a high success rate.

● Helped created tests, using L-edit to layout as well as checking the DRC by Cadence, and evaluate in-house reliability issues such as HCI, TDDB, and thermal cycles for many devices.

● Sustaining current processes by evaluating ET’s, tweaking tests, and run DOE/creating options for general process improvement.