• Developed co-simulation framework that interfaced C or Python program to SystemVerilog using DPI-C.

• Implemented pseudo PCIe device driver that interface between FPGA simulation and software test codes.

• Designed prototype class for magic ring buffer in C++.

• Developed Hardware Implementation of New Hope post quantum key exchange protocol on FPGA

• Implemented Number Theoretic Transform (NTT) computation circuit with Verilog

• Improved design for modulo prime 12289, which may output modulo value in three cycles.

• Verified design with Python Sage

• Developed scheduling recommendation system for Halide, an image processing language, with C++

• Cross-compiled recommendation program achieved about 15% speed improvement on arm-based mobile processor core

Embedded Multimedia Components and Transport System Lab

Advisor: Chun-Jen Tsai

• Implemented a HSAIL-liked instruction set architecture processor on FPGA

• Redesigned an open source processor core, Openfire, to accept HSAIL-liked instruction set architecture

• Modified Verilog code with pipelining and achieved at least 100MHz working frequency on Zedboard