• Developed DDR4 SDRAM Controller by using Questa.

• Identified the root of causes of current design problems in 3 days , by reading source System Verilog code.

• Use Vivado & Questa to simulate.

• Took Xilinx SDSoC Adopter Class.

• Identified ZCU104 Board Interface Test (XTP498) problem.

• Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit to verify.

• MIMD array of RISC-V, shared memory, OpenCL 1.2, OpenMP, ML.