# Wen-Jei Ho

> Senior engineer consultant at Raytheon

Location: Saratoga, California, United States
Profile: https://flows.cv/wenjei

Professional Experience:

FPGA, ASIC, Verilog, VHDL, RTL, STA, Digital, MATLAB, Simulink, SERDES, 8b/10b, PHY, Fiber Channel Framer, XAUI, 10 Gig-bit Ethernet Mac, Mixed Signal SOC, Spectrum Analyzer, SmartBits, Chariot, PumpKIN, Etherreal, AXI, PCI, PCIe, SPI, UART, RADAR, Logic Analyzer, ModelSim, Debussy, Radio Frequency (RFIC), GMII, OrCad, SDRAM, DDR, BIST, DFT.

Goal:Deliver one pass (zero spin) reliable design.

Most of my ASIC/FPGA design has BIST and Lab bring up tool logic to ensure quality.
In Cisco, OC48 ATM Line-card, there was a ordering rule bus racing problem. Use debugger, it never came. Use Logic Analyzer, couldn’t find trigger point to isolate it. I invented a way to isolate and resolve the problem.

Specialties: Many of my ASIC/FPGA design already in the market and some of them are flying with Fighter Jets.
Math, Logic, System Architecture, DFT, and troubleshooting are my strength.

Xilinx AXI/Zynq architecture is basically my patent in IBM, CMI (Common Module Interface):
http://www.google.sc/patents/US5845072
AXI interconnect IP core module is basically my "Freeway Concept Module" idea in IBM.

## Work Experience
### Engineering Consultant @ Northrop Grumman
Jan 2022 – Jan 2023

### Engineering Consultant @ Quanergy
Jan 2022 – Jan 2022 | Sunnyvale, California, United States

### VP of Engineering @ AI Plus Tech
Jan 2021 – Jan 2022 | San Jose, California, United States
- Developed DDR4 SDRAM Controller by using Questa.
- Identified the root of causes of current design problems in 3 days , by reading source System Verilog code.

### Senior engineer consultant @ Raytheon
Jan 2019 – Jan 2019

### Consultant Senior @ NXP Semiconductors
Jan 2018 – Jan 2018 | San Jose, California
• Use Vivado & Questa to simulate.
• Took Xilinx SDSoC Adopter Class.
• Identified ZCU104 Board Interface Test (XTP498) problem.
• Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit to verify.
• MIMD array of RISC-V, shared memory, OpenCL 1.2, OpenMP, ML.

### Senior Consulting Engineer @ BD-GenCell Biosystems
Jan 2017 – Jan 2017 | 2350 Qume Drive, San Jose, CA USA
Two to three months contract.

### Senior Consulting Engineer @ Lockheed Martin
Jan 2015 – Jan 2015 | Palo Alto, CA
•Virtex-7, XAUI and 10 Gig Mac loop-back running in the LAB no error.
•Use Vadatech/amc516, VePAL TX300s to test and ChipScope to debug.
•Packet Processor Unit (PPU) Loop-Back fully functional in the LAB.

### Senior Engineer Consultant @ Intel Corporation
Jan 2014 – Jan 2015 | San Jose
•Virtex-5, VHDL 500 MHz for DDR3 SDRAM Trace System.
•Use DPO70604B, Digital Phosphor Oscilloscope to debug.
•Use ChipScope to debug.

### Senor Engineer Consultant @ Total Phase
Jan 2014 – Jan 2014 | 735 Palomar Ave Sunnyvale, CA 94085
http://www.totalphase.com/products/promira-serial/
•Use Zynq, MicroZed, SDK.
•Create a new IP project, Customize the IP with MMCM DRP.
•Add it to the Vivado IP Catalog. Entire design tested working.
Xilinx AXI/Zynq architecture is basically my patent in IBM, CMI (Common Module Interface):
http://www.google.sc/patents/US5845072
AXI interconnect IP core module is basically my "Freeway Concept Module" idea in IBM.

### Senor Engineer Consultant @ Trango Systems
Jan 2013 – Jan 2013
•Point to point WiFi Encryption and Decryption (CFB128).
•Use Broadcom BCM85620. Designed glue logic talks to AES Helion.
•Successfully modified AES Helion IP Core Wrapper to meet Trango requirement.
•Created 100% self checking ModelSim test bench with well covered test case.
•Xilinx Spartan-6 device xc6slx25, package csg324, speed -3.

### Senior Engineer Consultant @ Intel Corporation
Jan 2013 – Jan 2013
•Virtex-5, VHDL 500 MHz for QPI and DDR3 SDRAM Trace System.
•Use DPO70604B, Digital Phosphor Oscilloscope to debug.
•One source for 6 FPGA's and they communicating one another.

### Senior FPGA Engineer Consultant @ SerialTek
Jan 2012 – Jan 2012 | San Jose
•Fixed Xilinx app-note (xapp 743).
•Allow Microblaze MCS to do PCIe gen-3 eye-scan for KC705 board.
•KC705 board Si570 Programming.
•Changed Transceiver from 3.125Gbps to 6Gbps.
•Changed reference clock from 156.25 MHz to 300 MHz.
•Add Timer in Verilog/TCL/C to allow very acurate performance measurement.
•One month contract to deliver eye diagram. It ends up delivered eye diagram, 6Gbps and very acurate performance measurement..

### Senior FPGA Engineer Consultant @ Xilinx
Jan 2011 – Jan 2012
•Virtex-7 PCIe Python Class code, for eye scans testing.
•Developed Xilinx "MCS to DRP" app-note (xapp743).
•ML605 board EDK, embedded system development training 2/22/2012.

### Senior FPGA Engineer @ OCZ Technology
Jan 2010 – Jan 2011
•Designed and verified DDR3 SDRAM Controller in Verilog.
•Architect SATA-3 RAID-0 Bridge FPGA, with NCQ and Trim.
•Read Serial ATA Revision 3.0, June 2, 2009, Gold Revision,
•Read ATA/ATAPI Command Set (ATA8-ACS)
•Read Serial ATA Revision 2.6, February 15, 2007
•Read ONFi Standard. Read LDPC books and papers.
•Investigate many SATA-Device and SATA-Host IP.
•Architecture and effort estimates for two SSD projects.

### Senior FPGA Engineer @ Chang Industry nc.
Jan 2009 – Jan 2010
•Fixed old FPGA (Virtex 5, xc5vlx110,ff1153), FFT for Radar, intermit failure problems.
•FMCW Radar model in MATLAB/Simulink for RPG defense system.
•MATLAB/Simulink and ModelSim Co-simulation for FPGA.

### Senior FPGA Engineer @ TASEON Inc.
Jan 2008 – Jan 2009
•Designed FPGA to interface with Analog Device DSP 21262, DiCon Laser, SRAM, ADC, Temperature Sensor and SPI Flash AT45DB161D-SU for Optical Switch.
•Invented a new way to resolve big/little endian issue.
•PCI express system level simulation in ModelSim SE with 8b10b monitor.

### Digital Design Manager @ Trango Systems
Jan 2005 – Jan 2008
•Delivered point to point Wi-Fi product TrangoLINK Giga for Trango System in less than 6 months, defined on 10/18/2006 and cross link movie show on 04/05/2007 and Las Vegas Trade show on 05/22/2007.
http://www.trangosys.com/products/point-to-point-wireless-backhaul/licensed-wireless/trangolink-giga.shtml

•Designed my own Gig-bit Ethernet Mac Core, SPI Core, Framer, AVR, IXP425 Interface and UART for Wi-Fi Wireless Giga Ethernet with 8 T1.
•Design Framer with Ethernet LAN and T1 multiplexer technologies.
•Designed 66MHz PCI with DMA Engine, running well in two prototypes.
•Xilinx FAE told me that he got several customers having problem to run Xilinx PCI Core at 66Mhz and wondering if they could use my PCI core.
•Use MPC8555E PowerQUICC-III Integrated Communication Processor.
•Use Provigent PVG310, Wavesat MC236/256 point-to-point Modem.
•Use Xilinx Spartan-3 PCI Evaluation Kit as one of the prototypes board.
•In charge all the FPGA in the product lines of Trango System.
•Fix intermit failure problems (old products) reported from customs, 
•Use HFA3861/65 Direct Sequence Spread Spectrum baseband processor.
•Use SmartBits, Chariot, PumpKIN and Etherreal internet tools.
•Use ModelSim SE 6.2g, ISE 9.1i and Debussy 5.4v10 development tools.
•Use Tektronix TLA7012, TLA7AB2 & P6960 Logic/Spectrum Analyzer.

### Sr. Electrical Engineer @ Rockwell Collins
Jan 2002 – Jan 2005
•Design JSF (F35) Camera IO FPGA, EP1S20F484C5 (19K LE)
•Design F22 FOTR Data Processor (FDP) CPLD/VHDL for SMFD
•Design and debug F18 Camera RGB Interface, Xilinx CPLD XC2C256.
•Design VHDL function to draw Circle in Camera image (Graphic mixer).
•Invented an improved Video Graphic merge algorithm.
•Solved background foreground graphic merge problem.
•Use Digilent XC2XL circuit development platform
•Use Altera Nios-II Development Kit, SOPC (SOC of FPGA) Builder.
•Attended Mentor Graphic Mixed Signal SOC Design Workshop
•Mentor Graphic Radio Frequency (RFIC) Simulation Workshop
•Design Micro-Display FPGA/Verilog, Altera EP1K100FC256-1
•Use MATLAB for spatial nulling GPS receiver ASIC
•Use LSI Rapid Chip 250 slice, 4.5M Gate, 88 MHz
•Use DSP TMS320C6713-225 from Texas Instruments (TI).
•Design Video Demux, Xilinx CPLD Matrix XC95144XL device
•Design GMII (Gigabit Media Independent Interface)
•Design Video Interface FPGA, QuickLogic Ql3012
•Use QuickWork SpDE 9.5 tool
•Use Cypress CPLD CY37512P208-125NC and Warp 6.3 tool
•PCIX bridge FPGA/VHDL IP core integration and verification
•Design Flash/PCI, i2c, UART, 10/100 MAC/Ethernet VHDL
•Use Quartus-II 4.1, SignalScan, ModelSim, Simplicity, ISE 6.3
•Learned Interlacing, Gamma Correction, DCT, NTSC, PAL, MPEG

### Sr. Hardware Engineer @ Cisco Systems
Jan 1995 – Jan 2002
•Invented RAS Module to help achieving RAS goal
•Diagnostic Software development (C/C++), 9/2001-1/2002
•Designed entire PCI bridge Verilog (no vender logic) FPGA
•Use Xilinx VIRTEX-100E FPGA device for OC48 ATM router.
•Use FPGA Compiler 2 and Xilinx Express to make hex file.
•Design SDRAM DIMM (168/200 pins) controller ASIC
•Use Synopsis synthesize tool DC
•Use Motive (Prime Time) static timing analysis tool
•Designed ECC Verilog function
•Gigabit Ethernet Controller design verification
•DDR/SDRAM design verification
•Designed CRC32 Verilog function for ATM/AAL5 packets CRC
•Designed CRC16 Verilog function for IP cells CRC calculation
•SDRAM and ECC Specialist, design/Lab issues
•Use Vera, Specman, VeriCov, Debussy, Clearcase, NC and VCS
•OC12/OC48/OC192 packet over SONET design verification
•Identified JEDEC 200 pin DIMM standard oversight
•Identified a Cadence Verilog tool oversight

### Hardware Director @ PAD Systems
Jan 1995 – Jan 1995
•Chief architect & hardware design, LapTop (team of 10+ Engineers)
•Use OrCad to check out the chipsets wiring and debug the LapTop.
•Designed Power Management FPGA/VHDL for the LapTop

### Advisory Engineer @ IBM
Jan 1984 – Jan 1994
•Lead weekly meeting with 10+ Engineers (5 ASIC leaders) to define CMI
•Got patent (US5845072) for CMI (Common Module Interface)
•Designed FLASH controller for RAID-5 disk array controller ASIC
•Designed i960 controller VHDL for RAID-5 disk array controller ASIC
•Designed Freeway modules VHDL for RAID-5 disk array controller ASIC
•Cloned i960/VHDL RISC engine, support C/C++ for system simulation
•Designed 8/10 code encoder/decoder SERDES in VHD for Fiber Channel.
•Designed Automatically-configuring memory subsystem PLD
•Designed DMA with Byte Alignment.
•IDLC, ISDN, LAPD, 9370, AS/400 & 3174
•Micro Channel Interface ASIC (386 based) for 3174


## Education
### Master in EE
University of Miami

### Master in Physics related
National Taiwan University


## Contact & Social
- LinkedIn: https://linkedin.com/in/wen-jei-ho-281881
- Portfolio: http://www.trangosys.com/products/point-to-point-wireless-backhaul/licensed-wireless/trangolink-giga.shtml
- Portfolio: http://www.cisco.com/en/US/products/hw/modules/ps2710/products_module_installation_guide_chapter09186a0080104aa9.html

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Source: https://flows.cv/wenjei
JSON Resume: https://flows.cv/wenjei/resume.json
Last updated: 2026-04-13