# Xiaolue Lai

> R&D Engineer at Mentor Graphics

Location: San Jose, California, United States
Profile: https://flows.cv/xiaolue

Analog/RF, mixed signal circuit simulation and noise analysis. Oscillator/PLL macromodeling, fast simulation and phase noise analysis. Large scale circuit simulation with multi-threading and multi-processing.

Specialties: Harmonic balance, shooting, phase noise, oscillator, PLL, circuit simulation, analog mixed signal circuit, woodworking

## Work Experience
### engineer @ Startup
Jan 2021 – Present

### Software Architech @ Mentor Graphics
Jan 2016 – Jan 2021 | San Francisco Bay Area
Power analysis, IR drop simulation on distributed systems

### Sr. Principle Engineer @ Cadence Design systems
Jan 2015 – Jan 2016 | San Jose
RF simulation, transient noise simulation

### Engineer @ BlueWave Inc
Jan 2012 – Jan 2015
Developed parallel IR drop simulator for huge circuits with billion instances.

### Senior Member of Consulting Staff @ Cadence
Jan 2007 – Jan 2012
Research and develop RF analysis algorithms for Cadence Spectre-RF.

### Intern @ Berkeley Design Automation (BDA)
Jan 2006 – Jan 2007
Hierarchical harmonic balance simulation and oscillator macromodel extraction

### Intern @ Cadence
Jan 2006 – Jan 2006
Developed codes in Cadence Spectre circuit simulator for extracting phase domain macromodels for voltage controlled oscillators (VCOs), and use the macromodels for fast PLL simulation.

### Logic Design Engineer @ SandCraft, Inc
Jan 2001 – Jan 2002
Cache controller design for a MIPS CPU

### Software Designer @ Data Panel Inc
Jan 1999 – Jan 2000
Designed a configuration software that generates control parameters for Data Panel's DPX emergency vehicle control system using C++ language.


## Education
### University of Science and Technology of China

### Ph. D in Electrical Engineering
University of Minnesota


## Contact & Social
- LinkedIn: https://linkedin.com/in/laixl

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Source: https://flows.cv/xiaolue
JSON Resume: https://flows.cv/xiaolue/resume.json
Last updated: 2026-04-11