Leader of Infrastructure team including Parser team, Front-end team, and VerilogA team, to develop and maintain infrastructure related work and build database for circuit simulation, as well as hundreds of features based on the circuit database:
1) Parser to support Spice and Spectre netlist;
2) Elaboration including building circuit hierarchy and connection, and expression evaluation;
3) Kernel database including flatten and partition;
4) Circuit optimization including fold, compress, short, reduction, etc. to improve performance and reduce memory;
5) VerilogA compiler, including latest VerilogAMS LRM syntax support, VA database and elaboration, C code dump and dynamic library build, run time library support;
6) API development to integrate system into customer platform both for Linux and Windows;