Project management, ASIC design flow/methodologies, Low power design, Micro-architecture definition, RTL design optimization for gate count reduction. SOC includes embedded ARM Cortex M0/M4, Tensilica DSP processors with AHB/APB interfaces.
Experience
2021 — Now
2020 — 2021
2003 — 2004
2000 — 2002
Education
University of Miami
PhD
National Chiao Tung University