# Yao-Ching Liu Ph.D. > DDR/LPDDR micro architecture Location: Cupertino, California, United States Profile: https://flows.cv/yaoching Project management, ASIC design flow/methodologies, Low power design, Micro-architecture definition, RTL design optimization for gate count reduction. SOC includes embedded ARM Cortex M0/M4, Tensilica DSP processors with AHB/APB interfaces. ## Work Experience ### DDR PHY Chip Architect @ Synopsys Inc Jan 2021 – Present | United States LPDDR6, LPDDR5, DDR5 ASIC Developement ### Sr Principal ASIC design @ Northrop Grumman Jan 2020 – Jan 2021 | United States ### Engineering Director/Technical Executive @ Nuvoton Technology Corporation Jan 2004 – Jan 2020 | San Francisco Bay Area Design Sigma Delta Audio codec, Equalizer, ALC, SLIMbus, Soundwire, interpolation/decimation, sample rate conversion filters. Class-D amplifiers, ARM Cortex-M0 and M4 SOC, 8051+Bluetooth Baseband, Chipcoder, SLIC FXS, USB, DECT, Echo cancellation, FSK products. Implement Low power methodologies. Design/Power Compiler, Formality, LEC, Primetime, nLint, Scan Insertion. Timing Closure. Researches: Neural Networks, Machine Deep Learning, Fuzzy Logic control, ### Design Manager @ Fortemedia Jan 2003 – Jan 2004 | Cupertino ,CA DSP, USB, Bluetooth, 8051 design ### Sr. MTS @ Pluris Jan 2000 – Jan 2002 Design 35Gbits per port IP core router switching fabric. High-speed multicast. Leaky-Bucket, resource management, priority scheduling. ### Project Manager @ Allayer Jan 1998 – Jan 2000 10Mb/100Mb/1G Ethernet switches. 10Gb x 2 ports + 1G x 10 ports L2 search engine. MAC, VLAN, Trunking, multicast, scheduling, buffer management. ### Sr ASIC design engineer @ IDT Jan 1996 – Jan 1998 ATM 155Mb/second ABR SAR with PCI, Utopia interfaces. ## Education ### PhD in ECE University of Miami ### BS in Applied Mathematics National Chiao Tung University ## Contact & Social - LinkedIn: https://linkedin.com/in/yaochingliu --- Source: https://flows.cv/yaoching JSON Resume: https://flows.cv/yaoching/resume.json Last updated: 2026-04-13