Experience
2020 — Now
2020 — Now
San Jose, California, United States
Developing Testchip for 3DIC, HPC and mobile with the most advanced technology nodes of TSMC 5nm, 3nm, 2nm
• Implement CPU Subsystem and SOC Subsystem with EDA tools (DCG synthesis, VC Formality, VC SPYGLASS, VC LP and PrimeTime)
• Define low power specification with UPF and verify with VCLP
• Clock Domain Crossing (CDC) with Spyglass CDC
2019 — 2020
2019 — 2020
Boxborough, Massachusetts, United States
Semicustom Business Unit (SCBU) developing APU processor
• Create IP UPF at SoC level for low power integration and implementation
• Create UPF for Native Low Power (NLP) verification at the top level
• Low power static check (VCLP) for checking IP design vs. power intent UPF
• Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) checks for IP
• Logical Equivalence Checking (Formality)
2009 — 2018
Suwon, Korea
Responsible for Chipset Strategy
• Working on fundamental strategy, core technology road-maps for Application Processor, Communication Processor
• Proposing a power-budget of LTE baseband chipset and its sub-blocks considering various use-cases, battery lifetime requirement
• Estimating and managing energy consumption at terminal-level, chip-spec-level and RT/gate-level. Verifying it by silicon measure
• Enhancing system energy-efficiency by surveying and inventing new low-power technologies like adaptive voltage scaling
• Decision-making regarding SoC Architectures to meet the target performance with a sufficient margin, and trade-offs between area and power consumption
Responsible for Low Power Architect
• Designing Power Management Unit(PMU) with power/voltage islands, retention and isolation schemes, sleep/wake--up scenario, dynamic voltage-frequency scaling(DVFS) scheme for both hardware and software policy. All such contributions have been silicon-proven in mass-production
• Structural low power design of level shifter and isolation cell topology and associated rules
• Architectural analysis and development of digital power optimization logic and circuit
• Creating detailed architecture and implementation documents
• Developing the verification environment specific for low power use-case scenarios
• Low power verification from RTL to Gate-level netlist with low power intent concepts and languages (UPF or CPF)
• Power estimation and reduction tools(PowerArtist/PTPX) and structural low power verification tool(CLP)
• Power optimization in silicon validation coordinating with S/W team for low power
• Creating a 'Low-power RTL coding guide', an internal document to educate RTL engineers
2007 — 2009
Suwon, Korea
• Designing and developing RTL code using Verilog and work with DV team to develop test cases and debug
• Working with the physical design team in aiding the implementation of the functional blocks
• Usage of EDA tools including simulators(NCVerilog, Modelsim), synthesis tools(DC), timing(Primetime)
• Pre-silicon verification tasks such as reviewing the verification plan, and full-chip simulation plus debug
• Demonstrated track record or bringing logic designs into high volume productions
• Experience scripting language such as Tcl, Python
Education
University of Minnesota