* Manage Physical Tool and Optimization team to develop in-house tool and flow solutions for Sparc processor design physical implementation. Leverage EDA vendor tool features and make up the shortfalls with internal EDA developments. Developing tools cover the areas of custom controlled RTL to gate synthesis, structured relative placement, high speed grid based clock and hybrid clock network, custom design and sram detail router, design rule checking engine, HPC via pillar router, and regional/global interconnect buffer insertion.

* Interact with TSMC to enable physical design on advanced node technologies, including 10FF and 7FF. Attending quarterly technical review meeting at Taiwan since 2014. Work as the main contact person with TSMC in the physical design APR tool and flow area to develop tool features and reference flows for new technology nodes. Coordinate router tech file debugging and fixing between foundry and EDA vendor.

* Interact with Synopsys to evaluate and to enable ICC2 features in 10FF and 7FF technologies. Track and resolve issues from new development and hold 3-way communication with foundry to resolve ICC2 router feature and design rule coverage issues.

* Interact with Cadence to evaluate Innovus for 10FF technology design flow. Coordinate tool testing and qualification efforts across multiple teams

* Managed Design Closure Tools development team. (04/2006)

Supported microprocessor design team timing and integration activities.

* Developed floorplanning and placement tools

Relative placer; Pin placement and optimization; Data path pre-route

* Developed physical composition tools for power and clock distribution.

Power bus routing and stitching; Clock header insertion and routing; Clock gating; Scan stitching

* Developed optimization tool for timing closure and power optimization.

Repeater insertion and gate sizing; High fan-out net synthesis; Wire class optimization; Multi-Vt optimization; Architect in-house timing optimization framework

* Managed Physical Design Optimization development team. (01/2006)

Managed physical design QC and build team.

* Designed and implemented scan stitching tool. (2005)

Migrated tools to new geometry database infrastructure.

Enhanced and support floor planning tools. Provide training to new members.

* Enhanced and supported global router. (2004)

Worked on timing driven and buffering aware global routing.

* Enhanced and supported geometry data base used by all internal back end engines. (2004)

Designed new geometry database infrastructure.

* Designed an algorithm and implemented into a tool to optimally insert multiple stage flip-flop into interconnect trees for multi-cycle global interconnects. This tool potentially shorten a project tape out time by about 3 months. Received US patent for the flow (2004)

* Implemented metal filler in detail router which can fill in metals that connect to power rail with any pattern given by user. (2003)

* Implemented a GUI interface using Qt for router to interactively display overflow and metal density violations in design viewer. (2003)

* Implemented a bucketed-balanced interval tree data structure for detail router engine. The data structure outperform the C++ STL-based implementation by 3 to 4 time faster and achieved much less memory consumption. (2003)

* Developed third generation interconnect optimization engine. The engine interact with timer, routers, and placer by using buffer insertion, wire sizing, and driver sizing to optimize slack subject to slew, noise, and area constraints. (2002)

* Analyzed, developed, and supported second generation interconnect repeater insertion tool for UltraSPARC microprocessor design projects. Tool optimizing timing, area subject to slew constraint.