* Designed and implemented scan stitching tool. (2005)
Migrated tools to new geometry database infrastructure.
Enhanced and support floor planning tools. Provide training to new members.
* Enhanced and supported global router. (2004)
Worked on timing driven and buffering aware global routing.
* Enhanced and supported geometry data base used by all internal back end engines. (2004)
Designed new geometry database infrastructure.
* Designed an algorithm and implemented into a tool to optimally insert multiple stage flip-flop into interconnect trees for multi-cycle global interconnects. This tool potentially shorten a project tape out time by about 3 months. Received US patent for the flow (2004)
* Implemented metal filler in detail router which can fill in metals that connect to power rail with any pattern given by user. (2003)
* Implemented a GUI interface using Qt for router to interactively display overflow and metal density violations in design viewer. (2003)
* Implemented a bucketed-balanced interval tree data structure for detail router engine. The data structure outperform the C++ STL-based implementation by 3 to 4 time faster and achieved much less memory consumption. (2003)
* Developed third generation interconnect optimization engine. The engine interact with timer, routers, and placer by using buffer insertion, wire sizing, and driver sizing to optimize slack subject to slew, noise, and area constraints. (2002)
* Analyzed, developed, and supported second generation interconnect repeater insertion tool for UltraSPARC microprocessor design projects. Tool optimizing timing, area subject to slew constraint.